Mitsubishi Denki Kabushiki Kaisha

Naoto Andoh

Kazuhiko Nakahara

Takao Ishida

Akira Inoue

Yasuharu Nakajima

Kenji Hosogi

A semiconductor device includes a semiconductor substrate and an electrode disposed on a major surface of the semiconductor substrate. A via hole is formed on a center of the electrode so as to open from a surface of the electrode to a place under the surface of the semiconductor substrate. A via-hole foundation electrode for inhibiting diffusion from a metal layer is formed inside the via hole and on the surface of the electrode, a via-hole electrode is formed on the surface of the via-hole foundation electrode. A back via hole is formed on the back of the semiconductor substrate opposite to the major surface thereof, and opened from the back of the semiconductor substrate to the via-hole electrode. A back via-hole electrode is formed on the back of the semiconductor substrate including the inside of the back via hole.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor element, such as a field effect transistor, and an adjacent connection region including a via hole. A simple structure prevents leakage current from flowing from a p-type buffer layer to a source electrode of the field effect transistor through a backside electrode and a via hole upper electrode, avoiding degradation in the gate-source dielectric resistance. A groove having a depth extending from a surface of an n-type semiconductor layer through a n-type semiconductor layer and a p-type buffer layer isolates a field effect transistor from a via hole that extends from the surface of an n-type semiconductor layer to a second surface of a compound semiconductor substrate. The groove prevents leakage current from flowing in a backside electrode in the via hole.

Semiconductor device including via hole and isolating circumferential

A semiconductor device includes a semiconductor substrate; an active layer having a first surface and a second surface opposing each other and located on the first surface of the semiconductor substrate with the second surface of the active layer contacting the first surface of the semiconductor substrate; a recess structure at the first surface of the active layer and having a bottom within the active layer; a gate electrode on the bottom of the recess structure; a second surface drain electrode disposed on the second surface of the active layer adjacent the recess structure; and a source electrode disposed on the opposite side of the recess structure from the second. Consequently, even if the distance between the edge of the surface drain electrode gate electrode and the corner of the recess structure is reduced, a high gate-drain breakdown voltage can be realized.

Recessed gate field effect transistor

A switched line phase shifter includes at least three transmission lines having different electrical lengths disposed between an input terminal and an output terminal and connectable in parallel to each other, at least three input side FET switches for connecting and disconnecting the input terminal and the input ends of the transmission lines, and at least three output side FET switches for connecting and disconnecting the output terminal and the output ends of the transmission lines. As many signal transmission paths as transmission lines are produced between the input terminal and the output terminal by controlling the input side and the output side FET switches. When one of the signal transmission paths is selected as a reference and a signal is transmitted through the remaining at least two signal transmission paths, at least two different phase shift quantities are obtained in the phase shifter.

Switched line phase shifter

A field effect transistor signal switching device includes a semiconductor substrate including an active region; an input electrode disposed on the substrate and including a source electrode disposed on the active region and a source pad; first and second output electrodes respectively including first and second drain electrodes disposed on the active region; and first and second control electrodes disposed on the substrate for controlling the selective transmission of an input signal applied to the input electrode to the first and second output electrodes, the first and second control electrodes respectively including first and second gate electrodes disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads, and first and second connecting portions disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads. An input line is connected to the source pad, first and second collinear output lines perpendicular to the input line are connected to the first and second output electrodes, respectively, and first and second control lines are connected to the first and second gate pads, respectively. In one embodiment, the first and second control lines are disposed on opposite sides of the first output line and generally parallel to the input line. In another embodiment, the first and second control lines are disposed on opposite sides of the input line and generally parallel to the first and second output lines.

Field effect transistor signal switching device

A DPDT switch includes first and second output signal electrodes opposite each other in an active region on a semiconductor substrate, a third output signal electrode opposite the second output signal electrode in the same active region, and first and second input signal electrodes disposed respectively between the first and second output signal electrodes and between the second and third output signal electrodes, and first control signal electrodes respectively disposed between the first input signal electrode and the first output signal electrode and between the second input signal electrode and the second output signal electrode for switching a signal between the input and output signal electrodes, and second control signal electrodes respectively disposed between the first input signal electrode and the second output signal electrode and between the second input signal electrode and the third output signal electrode for switching an input signal from the first and second input signal electrodes to the second and third output signal electrodes. The DPDT switch including an FET switch in the single active region enables a large reduction in the area of a switching circuit and miniaturization of the device to a large extent.

High frequency double pole double throw switch

Inductive structures having low parasitic capacitances for direct integration in semiconductor integrated circuits. In one embodiment, a generally planar spiral winding is disposed on the surface of a substrate. An electrical connection to the internal end of the spiral is made through electrically conducting vias passing through the substrate. The spiral may be spaced from a substrate surface by a plurality of spaced apart electrically conductive posts having a staggered arrangement between adjacent windings of the spiral. A transformer includes two windings disposed on top of each other on a semiconductor substrate and separated by an electrically insulating film. The windings have a common central opening in which a magnetic material is disposed to improve the inductive coupling between the windings. The transformer may include two helical windings, one surrounding another, each formed with vias and electrical conductors, the inner winding being formed in and on a semiconductor substrate and the outer winding being formed on insulating films disposed on the substrate and extending through the films and substrate. A variable inductor includes inductively coupled spiral windings separated by an insulating film and a current control for controlling the current through one of the spirals and, thereby, the effective inductance of the other spiral.

Growing community of inventors

Itami, Japan

Naoto Andoh