Nec Electronics Corporation

Nec Corporation

Naotaka Maeda

Masaharu Mizuno

Hideyuki Emura

Koichi Sato

Masamichi Kawarabayashi

Hitoshi Kurosaka

Shigeki Sakai

An ASIC includes a function layer formed with plural universal logic cells, a common layer formed with conductive strips connected to the universal logic cells and common to other ASICs and a customized layer having at least two metallization layers assigned to conductive strips extending in certain directions parallel to one another and other conductive strips extending in perpendicular directions to the certain directions, respectively, and an inter-layered insulating layer formed with conductive plugs selectively connected between the conductive strips and the other conductive strips, wherein the conductive strips have respective values of length such that the conductive plugs are located on both ends thereof, whereby the conductive strips, other conductive strips and the conductive plugs form plural signal paths reduced in total contact resistance and parasitic capacitance.

Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign

The master slice type semiconductor integrated circuit includes sequential circuit cells ( ) and combinational circuit cells ( ), which are alternately arranged in an inner core area on a semiconductor chip ( ), and a plurality of selective driving elements (MC to MC , MC to MC and MC to MC ), which are connected in a shape of a tree, for selectively distributing a poliphase clock signal for each division area formed by uniformly dividing the inner core area. The plurality of selective driving elements are placed and connected on the semiconductor chip such that load and wiring length between the sequential circuit cells within the respective division areas and input terminals to which the poliphase clock signal is inputted are equal. Due to this configuration, it is possible to cope with a poliphase clock, and also possible to reduce a clock skew between circuits, and further possible to provide a master slice type semiconductor integrated circuit in which an electric power consumption can be reduced.

Semiconductor integrated circuit and its layout method

A delay optimization system including a layout processing unit for receiving the input of circuit specification of a target circuit to conduct layout, as well as extracting wiring information, an optimization processing unit for conducting optimization with reference to the wiring information, as well as generating circuit change information and inserted buffer information, and a constraints violations determining unit for determining whether a circuit generated as a result of the layout by the layout processing unit satisfies delay constraints set for the target circuit, the layout processing unit executing initial layout based only on circuit information synthesized based on the circuit specification of the target circuit and re-layout with reference to the circuit change information and inserted buffer information generated by the optimization processing unit.

Delay optimization system to conduct optimization for satisfying delay

A logic circuit verification device comprising a data input section to read the circuit data and the circuit information of the logic circuits to be verified and converts them into the intermediate format, a corresponding point detection section to extract and output the information about the corresponding points using the corresponding point detection algorithm, a circuit partitioning section to read the intermediate format data and partition the logic circuits according to the corresponding point information obtained by the corresponding point detection section so as to prepare circuit data of the subcircuits and a equivalence checking section to read the circuit data of the subcircuits, determine the subcircuits to be compared with referring to the corresponding point information obtained by the corresponding point detection section and comparatively compares the circuit data of the subcircuits.

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Tokyo, Japan

Naotaka Maeda