Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Hitachi Engineering Co., Ltd.

Hitachi Microcomputer System, Ltd.

Naotaka Hashimoto

Shuji Ikeda

Toshiaki Yamanaka

Hiromi Abe

Shinichi Fukada

Hiroshi Momiji

Masayuki Suzuki

Satoshi Meguro

Atsuyoshi Koike

Koichiro Ishibashi

Yoshio Sakai

Yutaka Hoshino

Masanori Kojima

Takashi Hashimoto

Toru Kaga

Nobuyuki Moriwaki

Katsuro Sasaki

Soichiro Hashiba

Isamu Kuramoto

Yutaka Kobayashi

Tokuo Kure

Atsushi Hiraishi

Osamu Minato

Seigou Yukutake

Eiji Takeda

Shigeru Takahashi

Shinji Nishihara

Yoshifumi Kawamoto

Norio Suzuki

Makoto Motoyoshi

Kiyofumi Uchibori

Shigeru Honjou

Akihiro Shimizu

ShinIchiro Kimura

Kyoichiro Asayama

Shinichiro Kimura

Katsuhiro Shimohigashi

Masayuki Kojima

Toshiaki Masuhara

Sadayuki Morita

Takashi Nishida

Shoji Hanamura

Kazuyuki Suko

Fumiyuki Kanai

Yasuo Kiguchi

Toshiro Aoto

Eri Fujita

Masayuki A Suzuki

Toshihiko Tanaka

Norio Hasegawa

Yasushi Sasaki

Yasuko Yoshida

Toshifumi Takeda

Keiichi Yoshizumi

Kazushi Fukuda

Yasuhiro Sugawara

Shigeru Honjo

Kiyotsugu Ueda

Shigeru Honjyo

Shimpei Iijima

Satoru Haga

Eri Okamoto

Hiroshi Ishida

Nagatoshi Ohki

Yuuki Koide

Yaichirou Miura

Toshikazu Matsui

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Method of fabricating semiconductor integrated circuit device

In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

Method of manufacturing semiconductor integrated circuit device having capacitor element

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method of fabricating semiconductor device

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method for fabricating semiconductor device

Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Semiconductor integrated circuit device having capacitor element

Growing community of inventors

Koganei, Japan

Naotaka Hashimoto