Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Naoshi Yanagisawa

Shiro Dosho

Masaomi Toyama

Shiro Sakiyama

Hidehiko Kurimoto

Masayuki Ozasa

Tatsuo Okamoto

Keijiro Umehara

Takuji Miki

Toru Iwata

Takashi Morie

Masahiro Fukui

Kazuo Matsukawa

Takefumi Yoshikawa

Seiji Watanabe

Toshiaki Ozeki

Kazuaki Sogawa

Takahiro Bokui

Yuji Yamada

Kazuhiko Nishikawa

Ryoichi Suzuki

A capacitor array includes a plurality of comb capacitors sharing a common comb electrode. At least one of the comb capacitors has a comb electrode as a single base part. Each of the other ones of the comb capacitors has an electrode formed by coupling a plurality of base parts. In the other ones of the comb capacitors, a space between a wire coupling the base parts and an end of each of comb teeth of the common electrode, which is interposed between the base parts, is larger than a space between a base of each of the base parts of the plurality of comb capacitors and an end of each of the comb teeth of the common electrode, which is interposed between comb teeth of the base part.

Capacitor array and signal processor including the array

A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Reference voltage stabilizer circuit and integrated circuit including the same

A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.

Successive approximation AD converter

A constant determination unit () determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (), the time constant of a loop filter (), and the gain of a voltage controlled oscillator (), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (), the loop filter (), and the voltage controlled oscillator () modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit ().

Phase synchronizing circuit

An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.

Analog circuit automatic calibration system

The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means () for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element () included in the first filtering means () for allowing a first current to flow in accordance with the first voltage; current generating means () for generating a second current at a given rate to the first current; second filtering means () for accepting, as an input, the second current and outputting a second voltage; and adding means () for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit

In order to correct the duty cycle of a given clock signal to produce a clock signal with a 50% duty cycle, a duty cycle correction circuit includes a delay unit for delaying a first clock signal to output a second clock signal and a clock-signal output unit. The clock-signal output unit includes two transistors which use the first and second clock signals as the inputs of respective gates and an inverter circuit for inverting a signal output from a common drain of the transistors to output a third clock signal. The delay unit delays the first clock signal so that the first clock signal falling appears at a timing at which the duty cycle thereof becomes 50%. The two transistors in the clock-signal output unit output, as the third clock signal, a ground voltage and a source voltage as the signal from the common drain in response to the rising of the first clock signal and the falling of the second clock signal, respectively.

Duty cycle correction circuit

A semiconductor integrated circuit includes a plurality of units. Each of the units includes a power supply pad, a function circuit, and a power supply control circuit. The plurality of units each have a first state in which the function circuit is in an operating state by the power supply pad being at a prescribed operating potential and a second state in which the function circuit is in a non-operating state by the power supply pad being at a prescribed non-operating potential. The power supply control circuit includes a switching circuit for connecting the power supply pad to the prescribed non-operating potential. The power supply control circuit in each of the plurality of units closes the switching circuit when at least one of the other units is in the first state and opens the switching circuit otherwise.

Semiconductor integrated circuit

Fixed pattern noise of an analog memory is reduced. Transfer paths of an address selection signal (SL) between an address generation unit ( ) and respective storage elements ( ) for storing an analog signal are constructed to have a substantially uniform electric characteristic in driving the storage elements ( ) by the address selection signal (SL) to such an extent that the output signal of the analog memory is free from fixed pattern noise. A buffer unit ( ) for temporarily storing and outputting the address selection signal is provided between the address generation unit ( ) and the respective storage elements ( ), and the buffer unit ( ) is constructed to have an output characteristic substantially uniform between the storage elements ( ). Also, lines between the buffer unit ( ) and the storage elements ( ) are constructed to have substantially the same electric characteristic. In this manner, charge feed through noise of the respective storage elements ( ) are made substantially uniform, resulting in suppressing the fixed pattern noise.

Analog memory and image processing system for reducing fixed pattern noise

A jitter detector obtains a phase difference between input signals as a digital value to make jitter between the signals easily detectable. The jitter detector includes comparison pulse generator, periodic signal generator, counter and arithmetic unit. The comparison pulse generator outputs one phase difference comparison pulse after another. Each phase difference comparison pulse has a width representing the phase difference between first and second input signals. The periodic signal generator outputs a periodic signal every time a value obtained by accumulating the widths of the phase difference comparison pulses exceeds a predetermined value. Receiving the periodic signal and a clock signal with a period shorter than that of the periodic signal, the counter counts the number of pulses of the clock signal during one period of the periodic signal and outputs a resultant count. And the arithmetic unit detects and outputs a variation in the count as jitter between the first and second input signals.

Jitter detector, phase difference detector and jitter detecting method

An analog FIFO memory device allowing for the suppression of the adverse effects produced by fixed pattern noise, generated inside an analog FIFO memory, on signal components. First and second analog multipliers are respectively provided on the input and output sides of the analog FIFO memory. In synchronism with the inputs/outputs of signals to/from the analog FIFO memory, a non-inverting operation and an inverting operation are alternately and repeatedly performed on the input signals and the output signals. Then, although the signal input/output characteristics of the analog FIFO memory are not changed, the fixed pattern noise generated inside the analog FIFO memory is modulated by the second analog multiplier. As a result, the spectrum of the fixed pattern noise, which originally has a lower frequency, is shifted to have a higher frequency. That is to say, since a signal band can be separated from the fixed pattern noise in terms of frequency, the fixed pattern noise can be eliminated by a low pass filter. Consequently, even when the analog FIFO memory device of the present invention is applied for delaying TV signals, the resulting TV image quality is not deteriorated.

Analog FIFO memory device

A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.

Frequency detector and phase-locked loop circuit including the detector

A comb filter easily implementable as a monolithic LSI without using a large-capacitance capacitor is provided. A comb-like frequency characteristic is realized by two delay circuits for delaying a signal for mutually different amounts of time and an operation circuit for deriving a sum or difference of the outputs thereof. An input select switch selectively outputs, instead of an image signal, a test signal, which is a DC signal having a predetermined amplitude, during a blanking interval of the image signal. A detector controls the gain of a variable-gain amplifier, provided for the output of either one of the delay circuits, in accordance with a difference between the output signal of the comb filter in response to the test signal and a predetermined reference signal. That is to say, the gain of the comb filter is controlled by using a stable test signal as a control signal, instead of a burst signal contained in an unstable image signal. Accordingly, a large-capacitance capacitor, which has been required for stabilizing the control signal, is no longer necessary.

Comb filter and method for controlling the same

The invention provides an analog FIFO memory from which a written analog signal can be accurately read by eliminating errors in the analog signal between the write operation and the read operation. Prior to the read operation for reading the analog signal from a memory cell through a memory bus, a reset operation for setting the memory bus at a predetermined potential is conducted so as to remove a charge stored in a parasitic capacitance of the memory bus. The input terminal of a read circuit is set at a predetermined potential, with a write circuit disconnected from the memory bus by using an input circuit and with the read circuit connected with the memory bus by using an output circuit. In this manner, the memory bus is set at the predetermined potential, and the charge stored in the parasitic capacitance is discharged. At this point, a switch in each memory cell is in an off-state, and hence, a charge corresponding to the analog signal can be retained in the memory cell.

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Osaka, Japan

Naoshi Yanagisawa