Sony Corporation

Naoshi Ikeda

Toshio Kobayashi

Ikuhiro Yamamura

Hidetoshi Yamanaka

Takashi Emori

The present invention clarifies the conditions for the required element techniques to be technically superior and makes it easy to establish the development guideline during the development of a memory embedded semiconductor integrated circuit. The total resource CW of a fabrication technique is defined by utilizing the process number or mask number, etc., required for the fabrication; and the unit resource CWU is deduced by dividing the total resource CW with the effective wafer area; and the unit resource CWU multiplied by the area of the logic gate forming region is defined as the first effective technique resource CWL; that multiplied by the area of the memory cell forming region is defined as the second effective technique resource CWAM, that multiplied by the area of other regions is defined as the third effective technique resource CWP&IO; a plurality of techniques concerning the fabrication and/or design are compared by using the first to the third effective technique resources obtained as the above techniques are applied to, and from these techniques, those suitable to the required scales of the memory and the logic circuit are selected.

Memory embedded semiconductor integrated circuit and a method for designing the same

A semiconductor nonvolatile memory device using SA-STI cells improved in quality and suitable for increasing the degree of integration is provided with a semiconductor substrate having in its surface a channel formation region; an element isolation insulating film buried in a trench formed in the semiconductor substrate so as to divide the channel formation region into a plurality of regions; a gate insulating film formed on the channel formation region; a floating gate provided with a first floating gate formed at an upper layer of the gate insulating film and second floating gates formed at facing sides of the same; an inter-layer insulating film formed at an upper layer of the first floating gate and the second floating gates; a control gate formed at an upper layer of the inter-layer insulating film; and a source-drain region former connected to the channel formation region.

Semiconductor nonvolatile memory device and method of producing the same

A semiconductor memory device comprising a write transistor with a gate connected to a write word line and with a first impurity region forming a source or drain connected to a bit line, a read transistor with a gate connected to a second impurity region forming a source or drain of the write transistor, a first impurity region connected to a read word line, and a second impurity region connected to a bit line, and a capacitor connected between the gate and the second impurity region of the read transistor.

Semiconductor memory device

A semiconductor device comprising: a substrate, a gate insulating layer formed on the substrate, insulating isolation layers formed on each side of the gate insulating layer, an impurity diffusion region formed in the substrate beneath the insulating isolation layer, a first conductive layer formed on both the gate insulating layer and the insulating isolation layer, and an element splitting trench which split up at least the insulating isolation layer and the impurity diffusion layer into two parts respectively and form a trench in the substrate and is buried with conductive material.

Growing community of inventors

Kanagawa, Japan

Naoshi Ikeda