Nec Corporation

Renesas Electronics Corporation

Naoshi Doi

Takeshi Watanabe

Tsuneo Tsukagoshi

Itsuki Yamada

Yoshihiro Ono

Takumi Okamoto

A semiconductor integrated circuit design apparatus for analyzing a delay in a semiconductor integrated circuit. The semiconductor integrated circuit includes a delay analysis unit, a noise generation unit, a voltage fluctuation level analysis unit and a timing verification unit. The noise generation unit generates noise information based on a predetermined noise definition and the voltage fluctuation level analysis unit analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the generated noise information. Further, the timing verification unit makes the delay analysis unit analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis.

Semiconductor integrated circuit design apparatus and method for analyzing a delay in a semiconductor integrated circuit

An operation analyzing apparatus () for semiconductor integrated circuits according to this exemplary embodiment includes a simulation analyzing unit (), and the simulation analyzing unit () includes: a semiconductor characteristics extracting unit () that extracts the inductances L, resistances R, and capacitances C of a board, a package, and a semiconductor integrated circuit, from the semiconductor integrated circuit mounted on the board via the package; an individual network generating unit () that generates individual networks of the extracted inductance L, resistance R, and capacitance C with respect to each of said semiconductor substrate, said package, and said semiconductor integrated circuit; an integrated network generating unit () that generates an integrated network by integrating all of the generated individual networks; and an operation simulation running unit () that performs an operation simulation of the semiconductor integrated circuit by inserting a test noise pattern to an arbitrary position in the generated integrated network.

Method, apparatus, and system for analyzing operation of semiconductor integrated circuits

Growing community of inventors

Kanagawa, Japan

Naoshi Doi