Kabushiki Kaisha Toshiba

Naonobu Fujiwara

Hiroshi Yamazaki

Toshikazu Morisawa

Manabu Koarai

Takayuki Izumida

In a write process of compressed data &num;1, data transfer for one sector from a CPU to an HDD, and a local write for one sector by the HDD repeat themselves for 256 sectors. During the write process period, the system BIOS compresses data of the next data block by utilizing the period in which a local write is made by the HDD. That is, upon completion of data transfer for one sector, the system BIOS waits for completion of the local write for one sector by the HDD, and then transfers the next data for one sector. During that local write completion wait period, the system BIOS compresses the next data.

High-speed hybernation

In an initialization operation of a system, an I/O trap SMI is issued to a CPU, and CPU state map information is stored in a predetermined area in an SM-RAM. When an interrupt control process occurs during the activation of an OS, the CPU state map information formed in the initialization operation is set in the CPU, and the CPU operation mode is changed to an original mode in which interrupts from various I/O devices are enabled. In the original mode of the CPU, parallel processing using an interrupt is executed. Initialization commands are sequentially issued to a plurality of devices such as a KBC, an HDD, and a display controller. The KBC, the HDD, and the display controller generate command completion interrupt signals upon completion of the command processes for their initialization operations. Next commands are sequentially issued to devices which have generated the command completion interrupt signals. A plurality of devices are initialized in accordance with the command completion interrupt signals from these devices.

Growing community of inventors

Tokorozawa, Japan

Naonobu Fujiwara