Fujitsu Corporation

Naonobu Fujimoto

Takeo Fukushima

Yoshiaki Yato

Masakazu Mori

Sakutaro Sato

Koichi Nishimura

Kazuo Yamane

Kenji Sato

Kazuo Takatsu

Yoshinori Nakamura

Masanori Arai

Yukio Suda

Hatsumi Iino

Takahiro Furukawa

Katsutoshi Miyaji

Kenji Satoh

Nobuhide Yamaguchi

Takashi Kihara

Tetsuro Murase

Masami Mizuguchi

Takashi Yorita

Provision is made of a phase-locked loop circuit including a voltage-controlled oscillator, a phase comparator, and a low-pass filter, a pulse-cancelling processing unit, a pulse-cancelling control unit, and a divider circuit. By dividing the pulse-cancelling request signal of the pointer-action into several bits by the divider circuit, the pulse-cancelling control unit gradually changes the input phase to the phase comparator or the control voltage to the voltage-controlled oscillator in several stages from the state before the 1-bit pulse-cancelling to the state of the 1-bit pulse-cancelling so that the phase of the output clock signal from the voltage-controlled oscillator matches the 1-bit pulse-cancelled input clock signal. By this, phase control of the output clock signal is performed in units of less than 1-bit and jitter is suppressed.

Control method and apparatus for suppressing jitter

A communication system comprising at least one working system for receiving a signal from a source, at least one protection system for receiving the signal from the source, a detection part for detecting an alarm state of the signals received via the working system and the protection system and for outputting an alarm signal if the alarm state is detected in at least one of the working system and the protection system, a switching part for selectively outputting the signal received via one of the working system and the protection system in response to a control signal which determines a connection of the switching part, and a control part for supplying the control signal to the switching part based on the alarm signals from the detection part. The control part disregards the alarm signals if the alarm signals are generated from the detection part with respect to the working system and the protection signal approximately at the same time.

Duplexed communication system

A system for optical communication between first and second optical terminal stations, containing a plurality of working optical transmission lines each for connecting between the first and second optical terminal stations, a protection optical transmission line. Each of the first and second optical terminal stations contains a plurality of working pieces of optical terminal equipment, connected to the respective working optical transmission lines, a protection piece of optical terminal equipment connected to the protection optical transmission line, and a plurality of bidirectional optical signal paths, provided corresponding to the respective working pieces of optical terminal equipment, and each operative to connect the corresponding working piece of optical terminal equipment to the protection piece of optical terminal equipment.

Switching system of optical transmission lines for protecting from

Drop/insert channel selecting system

A pulse insertion circuit alternately distributes serial input data at a predetermined data clocking rate into first and second parallel input data, which are synchronously and simultaneously written into and read from a memory, the second input data as read being delayed by one bit. A selection means selects between the second input data and the one-bit delayed second input data and further switches between and establishes either a direct or a cross connection between the selected one of the second input data, as read or as delayed, and the first input data and the first and second output terminals thereof, at which there are produced, correspondingly, parallel and selected, first and second input data. A control means responds to a pulse insertion request to inhibit memory read-out by one read clock period and to control the switching means selectively to switch between the direct and cross-connections, the pulse addition being made to one of the parallel and selected, first and second input data, as specified by the pulse insertion request. Pulse insertion thus is performed at one-half the predetermined clocking rate, the selected and parallel, first and second input data with the required pulse inserted in the specified one thereof, thereafter being multiplexed and transmitted at the predetermined clocking rate.

Pulse insertion circuit

A stuff (or dummy) pulse and a stuff designation pulse which indicates existence of nonexistence of the dummy pulse are inserted in a multiplexed pulse code modulation signal to convert an input signal frequency to a higher frequency. The frame synchronization pulse is used as the stuff designation pulse. Therefore, stuff designation is possible even when the frequency difference between the input signal frequency and output signal frequency is small.

Frequency converter

A hierarchical data transmission system outputs a high speed second data train by step-by-step multiplexing a plurality of first data trains. A first signal processing part operates at the processing speed corresponding to the first data train, a third signal processing part operates at the processing speed corresponding to the second data train, and a second signal processing part operates at the processing speed corresponding to the intermediate speed of the first data train and second data train. A first clock signal of the speed corresponding to the processing speed of the third signal processing part, a second clock signal of the speed corresponding to the processing speed of the second signal processing part by dividing the first clock signal, and a third clock signal of the speed corresponding to the processing speed of the third signal processing part are generated the first signal processing part operates in association with the third signal processing part, by dividing the second clock signal after the phase adjustment with reference to the phase information of the first clock signal.

Hierarchical data transmission system

Multiplex system for replacing a faulty multiplexer output with an

A frame synchronizing circuit uses parallel processing of a received multiplexed signal to detect frame synchronization. The input signal is separated into a predetermined number of signal trains. A matching number of frame synchronizing pattern detection circuits detect the presence of the frame synchronizing pattern by each of the frame synchronizing pattern detection circuits detecting the presence of a modified frame synchronizing pattern. The modified frame synchronizing patterns all contain the same sequence of bits, but the leading bit of the frame synchronizing pattern is in a different signal train in each of the modified frame synchronizing patterns. Timing comparison circuits corresponding to the modified frame synchronizing pattern detection circuits indicate which, if any, of the modified frame synchronizing patterns, are in coincidence with a frame pulse generated at the time the frame synchronizing pattern is expected to be detected. Synchronization guarding circuits corresponding to the timing comparison circuits indicate which, if any, of the modified frame synchronizing patterns is in synchronization with the frame pulse. A timing control circuit adjusts the timing of the frame pulse when the timing comparsion and synchronization guarding circuits indicate noncoincidence and asynchronization of all of the modified frame synchronizing patterns.

Frame synchronizing circuit

A hierarchical data transmission system is comprised, on the transmitter side, of pre-group multiplexers and a main-group multiplexer and, on the receiver side, of a main-group demultiplexer and pre-group demultiplexers. The main-group multiplexer is fabricated as a parallel-serial converting unit, and the main-group demultiplexer is fabricated as a serial-parallel converting unit. Each of the pre-group multiplexers produces a pre-group data train having a sub-data signal which is also utilized for distinguishing one pre-group data train from another. Each of the pre-group demultiplexers is provided with a discriminator operative, by using the sub-data signal, to distinguish one received pre-group data train from another.

Growing community of inventors

Kawasaki, Japan

Naonobu Fujimoto