Fujitsu Corporation

Naomi Yamazaki

Ryoetsu Nakajima

Takumi Maruyama

Kiyoshi Sugita

Masumi Fujino

An input data (input frame) is sequentially stored in memory in time slot units. A counter counts the number of input pulses of a clock synchronous with the time slot of the input frame, outputs the count value as a write address to the memory, and outputs it as a read address to the memory. A processor in a cross-connection device preliminarily writes to the memory data indicating switching information of a time slot. The memory outputs the data stored at an address input from the counter as a read address to the memory. The memory outputs data of a time slot of an input frame stored at the address as time slot data of an output frame.

Cross-connection switch

The present invention relates to a mounting-state display apparatus for displaying the mounting-states of devices. Particularly, the present invention provides a mounting-state display apparatus enabled to automatically generate a display, indicating the mounting-states of various kinds of packages in the devices, which is not limited to a specific device, by using an NE-OPS for managing the devices. This mounting-state display apparatus comprises a device component database, for holding device components, which represents a mounting state of an arbitrary one of the devices as original picture elements of a minimum configuration required to indicate a mounting-state display and an application program portion for accessing the device component database and for generating a display indicating the mounting state of a specific one of the devices by performing operations of placing the original picture elements and changing the size thereof.

Apparatus for displaying mounting state of device

A bus control device having a plurality of devices such as a processor or a DMAC which can be a bus master accessing a system bus. When the processor transfers data to a memory or a processing circuit, a system bus controller for the processor and a system bus controller for the memory or a system bus controller for the processing circuit access the system bus within an accessible minimum time with each of input/output signals. When the DMAC transfers data to the memory or the processing circuit, a system bus controller for the DMAC and the system bus controller for the memory or the system bus controller for the processing circuit access the system bus within the accessible minimum time with each of the input/output signals.

Control for timed access of devices to a system bus

When normal data is written to a desired address in a DRAM, a guarantee bit comparing/generating circuit sets the value of guarantee bit data stored at the address corresponding to the desired address in a DRAM as a value indicating that the normal data has been written. Since the guarantee bit data stored at each address in the DRAM always becomes '000' or '111' immediately after power is turned on, the above described value indicating that the normal data has been written is set as a value other than '000' and '111'. Thereafter, if the value of the guarantee bit data stored at the address corresponding to the desired address in the DRAM indicates that the normal data has been written when the normal data is read from the desired address in the DRAM, the normal data read from the DRAM is output to a data bus. Otherwise, the fixed value '0' is output to the data bus as read data.

Memory initialization system selectively outputting a data between a

A firmware trace data acquisition method is constituted such that there are provided a monitoring part for monitoring firmware processes and a DMA part for transferring data to a trace data storing part in accordance with an instruction from the monitoring part, such that labels are attached to the plurality of process modules stored in a firmware storing part, and such that each of the process modules activated notifies the monitoring part of the label attached to itself. The monitoring part latches the label that it is notified of and monitors the execution of the corresponding process such that, when an abnormality is detected during the execution, the monitoring part controls the DMA part so as to transfer detailed data, derived from the process module corresponding to the label latched, to the trace data storing part, and such that, when there is no abnormality detected, the monitoring part allows the DMA part to transfer the latched label to the trace data storing part.

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Kanagawa, Japan

Naomi Yamazaki