Kioxia Corporation

Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Naomi Takeda

Masanobu Shirakawa

Marie Takada

Hiroshi Yao

Akio Sugahara

Ryo Yamaki

Hideki Yamada

Tokumasa Hara

Yoshihiro Ueda

Shinichi Kanno

Hiroshi Sukegawa

Yasuhiko Kurosawa

Kenta Yasufuku

Kenji Sakurada

Daiki Watanabe

Daisuke Iwai

Yu Nakanishi

Arata Miyamoto

Yasuyuki Ushijima

Yuta Aiba

Noboru Shibata

Kenichiro Yoshii

Osamu Torii

Kengo Kurose

Takahiro Shimizu

Akira Yamaga

Naoaki Kokubun

Shozo Isobe

Ikuo Magaki

Naoto Oshiyama

Masami Aihara

Takashi Nakagawa

Seiichi Nishio

Yuichiro Matsuoka

Shingo Yanagawa

Manabu Sato

Lanyin Hsu

According to one embodiment, a memory system includes 1st-5th sub-memory regions and a controller, the controller being configured to: calculate a 1st voltage of the 1st sub-memory region in 1st processing; calculate a 2nd voltage of the 4th sub-memory region in 2nd processing; before the 1st processing, use a 3rd voltage when reading the 1st and 2nd sub-memory regions, and the 4th and the 5th sub-memory regions, and use a 4th voltage of the 3rd sub-memory region when reading the 3rd sub-memory region; use the 1st voltage when reading the 1st sub-memory region, use a 5th voltage calculated by using the 1st voltage when reading the 2nd, the 4th, and the 5th sub-memory regions, use a 6th voltage calculated by using the 2nd voltage when reading the 2nd and the 5th sub-memory regions.

Memory system

According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.

According to an embodiment, a controller acquires a first temperature detection value and executes an acquisition operation on a first storage area. The controller converts a first voltage value into a second voltage value representing the read voltage in a temperature set value based on the first temperature detection value and records the second voltage value. The acquisition operation is an operation of determining, by using the read voltages, whether memory cells are ON or OFF and acquiring the first voltage value representing the read voltage for suppressing error bits. After that, the controller acquires a second temperature detection value and converts the second voltage value into a third voltage value representing the read voltage in the second temperature detection value. The controller reads data from the memory cells by using, as the read voltage, a voltage indicated by the third voltage value.

Memory system and method

According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

Memory system and memory device

According to one embodiment, a memory system includes a non-volatile first memory with first storage areas. A controller executes a first read operation on a second storage area of the first storage areas. When an error correction in the first read operation fails, the controller acquires a first measured value being a value of a read voltage for suppressing the number of occurrences of error bits in the second storage area. The controller updates, on the basis of the first measured value, one of first candidate values of the read voltage with a second candidate value. When the error correction in a second read operation for a third storage area of the first storage areas fails, the controller executes the read operation once or more on the third storage area by using, as the read voltages, different first candidate values of the first candidate values.

According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.

Memory system and shift register memory

A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

Memory system and memory controller

A memory controller according to an embodiment includes a control circuit configured to duplicate and store data received from an external host device. The control circuit is configured to, when a write request specifying first data and a first logical address is received: i) allocate a first physical address corresponding to a first bit to the first logical address, and order a first memory device to write the first data to the first physical address; and ii) allocate a first mirroring physical address corresponding to a second bit to the first physical address, and order a second memory device to write the first data to the first mirroring physical address. A number of reads the first bit is different from a number of reads for the second bit.

Memory controller, memory system, and information processing system

According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n&#xd7;j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n&#xd7;j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.

Memory system and information processing system

According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.

Growing community of inventors

Yokohama, Japan

Naomi Takeda