Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Naomi Miyake

Hiroshige Hirano

Makoto Kojima

Tatsumi Sumi

Hisakazu Kotani

An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

Redundant memory cell selecting circuit having fuses coupled to memory

A voltage level of an output node is reversed by an inverter. An output of the inverter is used as an initial setting signal. A feedback switching transistor is also provided in an initial value setting circuit. Furthermore, there is provided a limiting device for eliminating an abnormal operation of the feedback switching transistor until the inverter starts a normal operation, in the event of momentary power failure or when the electric power source is quickly turned on after a very short break. Accordingly, normal operation of the inverter is assured even in such an abnormal condition accompanying momentary interruption of power supply, thereby surely outputting an initial setting signal.

Initial value setting circuit

A current mirror is composed of N-MOS transistors N1, N2, a diode-connected P-MOS transistor P1 is connected to an output side of the current mirror, and a source of a P-MOS transistor P2 controlled according to the gate potential of the P-MOS transistor P1 is connected to a power source V.sub.CC via a polysilicon resistor R. The drain of the P-MOS transistor P2 is connected to the drain of the N-MOS transistor N2. A current-mirror-connected N-MOS transistor N3 is provided at the current mirror of the N-MOS transistors N1, N2. The output of the N-MOS transistor N3 is inputted to another current mirror composed, on the power source V.sub.CC side, of two P-MOS transistors P3, P4, a constant current is outputted from the drain of one of the two P-MOS transistors P3, P4 and received by a load circuit which is the series-parallel connection of diode-connected P-MOS transistors P5-P8, and the voltage generated at the load circuit is outputted as a reference voltage output V.sub.REF. Thereby a negative temperature dependency that the reference voltage V.sub.REF drops at high temperature and rises at low temperature is cancelled or is made positive.

Reference voltage generator

A random access memory includes a redundancy repair circuit having a plurality of parallel connected transistors and a plurality of fuses connected to respective drains of the plurality of transistors. An electrically resistive element is connected to a common node to reduce a difference in operating speeds between a first case in which the circuit is precharged from a state in which discharge to a low level was effected via one of the transistors and a case in which precharging of the circuit is effected from a state in which discharging was carried out via a plurality of the transistors.

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Kyoto, Japan

Naomi Miyake