International Business Machines Corporation

Naoko Pia Sanda

Jeffrey W Kellington

Steven H Voldman

Ronald Nick Kalla

Scott Barnett Swaney

Prabhakar Nandavar Kudva

Alan Weger

John Andrew Schumann

Todd Alan Venton

David F Heidel

Jerry Don Ackaret

Richard B Bhend

Jane Jones, Legal Representative

Techniques are provided for determining consequences of an injected fault on a system running a given application program or operating system, in order to measure the software impact of a hardware soft error on the application program/operating system. The application program software is emulated instruction-by-instruction, where source operands are randomly modified before an instruction is executed, and destination operands are randomly modified after an instruction is executed, in order to mimic hardware soft errors. In addition, a program counter is randomly modified after execution of a branch instruction. The resulting consequences of such modifications are monitored such that a fault of an instruction being executed is modeled in order to determine a soft error rate (SER) for a software application program or operating system.

Testing soft error rate of an application program

A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC.

Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulation

A method and system are provided for accelerated detection of soft error rates (SER) in integrated circuits (IC's) due to transient particle emission. An integrated circuit is packaged for accelerated transient particle emission by doping the underfill thereof with a transient-particle-emitting material having a predetermined emission rate. The emission rate is substantially constant over a predetermined period of time for testing. Accelerated transient-particle-emission testing is performed on the integrated circuit. Single-event upsets due to soft errors are detected, and a quantitative measurement of SER is determined.

System and method for accelerated detection of transient particle induced soft error rates in integrated circuits

A method, system and apparatus are provided for operating a Picosecond Imaging Circuit Analysis (PICA)/high current source system include applying pulses from a high current pulse source to a Device Under Test (DUT). A photosensor detects photon emissions from the DUT. Signals from the photosensor are used to map photon emissions from the DUT. Data processing means relate the photon emissions to specific features of the DUT.

Method and application of PICA (picosecond imaging circuit analysis) for high current pulsed phenomena

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Rensselaer, NY, United States of America

Naoko Pia Sanda