Hitachi, Ltd.

Elpida Memory, Inc.

Naoki Yamada

Kazuyuki Miyazawa

Hiroshi Sato

Tetsuya Tsujikawa

Kenichi Wada

In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Non-volatile multi-level semiconductor flash memory device and method of driving same

Non-volatile multi-level, semiconductor flash memory device and method of driving same

Nonvolatile semiconductor storage device

An information processing system having an instruction unit for decoding each of successive instructions to generate an address of a next instruction, and additionally, when a branch instruction is decoded, a branch-to address of the decoded branch instruction. An execution unit sequentially executes the decoded instructions and a plurality of registers are provided for storing the next instruction address and the branch-to address. A pointer is generated to indicate one of the registers in which the next instruction address or the branch-to address is to be stored and the pointer is changed sequentially and cyclically in response to a first signal which is generated by the execution unit upon completion of execution of each decoded instruction or a second signal which is generated by the execution unit upon success in branch when a branch instruction is executed. Further provided is a delay circuit for receiving the pointer and generating it at a predetermined time delay. The delayed pointer is latched at a timing predetermined by the first and second signals and an interrupt signal produced, upon detection of an interrupt request, at a timing determined in dependence on the type of the interrupt request, and the instruction address used for a program status word is read out of one of the registers indicted by the latched pointer.

Data processor adapted for interruption to an instruction stream

A data processing system using a store data buffer control device includes plural store data buffers and the data from a processor is temporarily stored in the store data buffers and then transferred to a memory. A shift register is used to trace the storing requests from the processor so that the storing requests re-executable in the instruction re-execution taking place at the time of a fault occurring are distinguished from the storing requests not re-executable in the same operation. The data held in the store data buffers corresponding to the re-executable requests is invalidated while the data held in the store data buffers corresponding to the non-re-executable requests is kept valid.

Store data buffer control system

Growing community of inventors

Sakado, Japan

Naoki Yamada