Kabushiki Kaisha Toshiba

Naoki Wakita

Sadayuki Yoshitomi

Yuka Itano

Fumie Fujii

Tetsuya Yamaguchi

Shigeyuki Hayakawa

An ESD protection circuit has a diode that includes an anode connected to a first power-supply line and a cathode connected to a second power-supply line. A metal-oxide-semiconductor (MOS) transistor is connected in series with the diode. A trigger circuit is configured to output a trigger signal to a gate of the MOS transistor in synchronization with a surge on the first power-supply line. A first resistor and a first capacitor are connected in series between the first power-supply line and the second power-supply line. A well region, in which the source and the drain of the MOS transistor are disposed, is connected to a connection point between the first resistor and the first capacitor. A potential of the connection point varies so that a forward voltage is applied to a p-n junction between the well region and the source of the MOS transistor to correspond with the surge.

ESD protection circuit

According to one embodiment, provided is a semiconductor device including a lower layer wiring, and an upper layer wiring that is drawn in the same direction as a direction in which the lower layer wiring is drawn. Intermediate wirings include at least a first intermediate wiring and a second intermediate wiring. Conductors include at least a plurality of first conductors connecting between the lower layer wiring and the first intermediate wiring, a plurality of second conductors connecting between the upper layer wiring and the second intermediate wiring, and a plurality of third conductors which connect between the first intermediate wiring and the second intermediate wiring, and are less in number than the first conductors or the second conductors on a drawn side of the lower layer wiring and the upper layer wiring.

Semiconductor device

A circuit simulation apparatus according to an embodiment of the present invention calculates a set value of a SPICE parameter of a MOSFET to carry out a variation analysis on a semiconductor circuit including the MOSFET. The apparatus includes a storage part configured to store an intermediate model expression that includes a variable related to a manufacture condition or device structure of the MOSFET as a variable affecting variation characteristics of the MOSFET, the intermediate model expression being formed with a universal function having a physical correlation between a physical amount defined by the variable and the SPICE parameter, a setting part configured to set information about the variable included in the intermediate model expression, a calculation part configured to calculate the set value of the SPICE parameter by using the information set in the setting part and the intermediate model expression stored in the storage part, and an output part configured to output process variation dependency of the semiconductor circuit.

Variation distribution simulation apparatus and method, and recording medium

In one embodiment, a SPICE corner model generating method for generating a SPICE corner model of an MOSFET includes preparing a table of a ratio X regarding a combination of two kinds of MOSFETs selected from N kinds of MOSFETs, the ratio X being a magnitude of a variation of an MOSFET in a case where directions of variations of the two kinds of MOSFETs are opposite directions to a magnitude of a variation of an MOSFET in a case where the directions of the variations of the two kinds of MOSFETs are the same direction, where N is an integer of 2 or greater. The method further includes reading out, when a combination of two kinds of MOSFETs is designated among the N kinds of MOSFETs, a value of the ratio X corresponding the designated combination from the table of the ratio X. The method further includes forming two kinds of corner models of opposite directional variations, the two kinds of corner models including a first corner model generated by applying the value of the ratio X to a fast-side corner of a first MOSFET of the two kinds of MOSFETs and to a slow-side corner of a second MOSFET of the two kinds of MOSFETs, and a second corner model generated by applying the value of the ratio X to a slow-side corner of the first MOSFET and to a fast-side corner of the second MOSFET.

Spice corner model generating method and apparatus

In the disclosed invention, the influence of the dispersions of the gate lengths and the gate widths is prevented from adversely affecting circuit parameters except for the specific circuit parameter. According to this invention, the circuit parameters can be correctly extracted, and circuit characteristics can be accurately predicted.

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Kawasaki, Japan

Naoki Wakita