Nippon Precision Circuits Inc.

Naoki Ueno

There is provided a D-type flip-flop circuit which is improved in terms of operating frequency. First and second current supplying circuits are provided as sources for supplying currents to first and third differential circuits for inputting data and to second and fourth differential circuits for holding data in a master circuit and a slave circuit. Further, timing for supplying the currents to the respective differential circuits for inputting and holding data are controlled by first and second clock signals, respectively. The D-type flip-flop circuit is improved in terms of operating frequency by optimizing timing for writing input data and timing for holding data by arranging the first clock signal so as to have a certain delay with respect to the second clock signal. Further, the D-type flip-flop circuit is improved with respect to the operating frequency also by optimizing the value of the currents supplied to the respective differential circuits.

D-type flip-flop circiut

A current supply circuit and bias voltage circuit is realized which is not dependent on temperature. A current supply circuit that operates independent of temperature is configured such that a control voltage is generated by amplifying a base-to-emitter voltage of a first transistor so that the control voltage is applied to a base of a second transistor for supplying an output current to a load connected to a collector. In an alternate bias voltage circuit embodiment, an output voltage that is not dependent on temperature is generated by a voltage drop due to a collector resistor connected to the collector of the second transistor.

Current supply circuit and bias voltage circuit

Increase of frequency and reduction of power consumption are advanced for a voltage controlled oscillation circuit. A capacitor C1 is connected between emitters of first and second transistors Tr1, Tr2 to receive an electric current from constant current sources Cs1, Cs2. Also, emitters of third and fourth transistors Tr3, Tr4 receive an electric current from a constant current source Cs3 and have their respective collectors connected through third and fourth resistors R3, R4 to a power supply terminal VCC. The respective collectors and bases of the third and fourth transistors Tr3, Tr4 are connected to bases and collectors of the first and second transistors Tr1, Tr2. Due to this, oscillation outputs are caused at respective ends of the capacitor C1, which has a voltage amplitude equal to a voltage drop due to the third and fourth resistors R3, R4 and values of currents flowing through them. The voltage drop can be decreased to such an extent that the first and second transistors Tr1, Tr2 can be turned on. Also, the voltage drop due to the first and second resistors R1, R2 and the current flowing through them can be decreased to such an extent that the third and fourth transistors Tr3, Tr4 can be turned on. This decreases the resistance value of each resistor and the value of the current flowing therethrough to thereby increase the operating speed and reduce power consumption.

Voltage controlled emitter coupled multivibrator circuit

There is disclosed a frequency divider that operates at an improved operating speed and provides frequency division given with a frequency division ratio of N, where N is an odd number. The frequency divider comprises first, second, and third stages of D-type flip-flops. The first stage selects either the output from the second stage or the output from the third stage according to the logic level of the output from the third stage. Delay is eliminated from between the first and third stages and from between the first and second stages. Consequently, the operating frequency can be enhanced.

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Tochigi-ken, Japan

Naoki Ueno