Nippon Telegraph and Telephone Corporation

Adv Antest Corporation

The University of Tokyo

Naoki Terao

Hideyuki Nosaka

Munehiko Nagatani

Masahiro Ishida

Toru Nakura

Takashi Kusaka

Kunihiro Asada

Rimon Ikeno

A delta sigma modulator includes: an integrator that integrates differences between input signals and output signals of the delta sigma modulator; and a clocked comparator that outputs the output signals that are results of comparison between an output of the integrator and a threshold, at a timing synchronized with a clock signal. The integrator includes an operational amplifier, input resistors, feedback capacitors, and compensation inductors.

Delta sigma modulator

A sampling circuit includes: a first transmission line that transmits an input signal; a second transmission line that transmits a clock signal; and a plurality of sample-hold circuits that are connected to the first and second transmission lines at a constant line distance, wherein the first transmission line transmits the input signal at a first propagation time for each of the line distances, and the second transmission line transmits the clock signal at a second propagation time that is a sum of a preset sampling interval and the first propagation time for each of the line distances.

Sampling circuit

A track-and-hold circuit includes: a transistor, in which a base is connected to a signal input terminal, a power supply voltage is applied to a collector, and an emitter is connected to a first signal output terminal; a transistor in which a base is connected to the signal input terminal, the power supply voltage is applied to a collector, and an emitter is connected to a second signal output terminal; capacitors; a constant current source; and a switch circuit alternately turning the transistors to an ON state in response to differential clock signals.

Track-and-hold circuit

Bias adjusting circuits (_(-),_) (where k is an integer equal to or greater than 1 and equal to or less than N, and N is an integer equal to or more than 2) adjust DC bias voltage of at least one of clock signals such that a duty ratio, which is a ratio between a period in which a clock signal is High as to a clock signal and a period in which the clock signal is Low thereasto, becomes (N&#x2212;+1):(&#x2212;1). Sampling circuits switch between a track mode in which an output signal tracks an input signal, and a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with clock signals output from the bias adjusting circuits (_to_N).

A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.

Switched emitter follower circuit

A power supply apparatus supplies a power supply voltage V. The power supply apparatus includes a compensation circuit in addition to a main power supply. The compensation circuit receives, via its input, as a feedback signal, a detection signal Vthat corresponds to the power supply voltage V. The compensation circuit has input/output characteristics fthat correspond to the characteristics of the main power supply and the characteristics of a target power supply to be emulated. The compensation circuit injects or otherwise draws a compensation current ithat corresponds to the detection signal Vto or otherwise from a node for generating the power supply voltage V.

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Tokyo, Japan

Naoki Terao