Sanyo Electric Co., Ltd.

Sanyo Semiconductor Co., Ltd.

Semiconductor Components Industries, LLC

Naoki Tanahashi

Shigeyuki Okada

Hayato Nakashima

Kensuke Fujimura

Noriaki Sakamoto

Hideki Mizuhara

Takaya Kusabe

Masahiko Mizutani

Tetsuo Kosuge

Tsuyoshi Hasegawa

Keita Kawahara

Yoshinari Sakuma

When data is an HDTV signal, a buffer memory is used as two banks and pipeline processing is performed. When data is an SDTV signal, on the other hand, the buffer memory is used as a bankless buffer memory, and the pipeline processing is not performed.

TV signal processing circuit

A lighting device including a metal substrate to prevent temperature rise of LED chip is offered. The lighting device includes the metal substrate, an anode or cathode electrode of the LED chip disposed on the metal substrate, brazing materials connecting the LED chip and the metal substrate, and a groove formed in the anode or cathode electrode. Forming the groove can prevent an occurrence of a crack in the brazing materials. Also, a lighting device includes the metal substrate, an anode and cathode electrode of the LED chip disposed on the metal substrate and brazing materials connecting the LED chip and the metal substrate. Further, a slit is formed in the metal substrate between the anode and cathode electrode. Forming the slit in the metal substrate can prevent an occurrence of a crack in the brazing materials.

Lighting device and method of manufacturing the same

There is disclosed a clock regeneration circuit having a PCR buffer including a register which buffers a PCR extracted from a transmission signal, a counter which counts a reception side reference clock CKr, an STC buffer including a register which buffers a counted value of the counter, and a CPU which generates a signal indicating a difference between a transmission side reference clock and the reception side reference clock CKr based on values held in the PCR buffer and the STC buffer. If, at this point, a new PCR is input before the values held in the PCR buffer and the STC buffer are read by the CPU, the PCR buffer and the STC buffer are not updated.

Clock regeneration circuit

A video decoding apparatus for decoding encoded video data to continuously produce decoded pictures. The video data includes a series of pictures, each picture contains a series of slices, and each slice contains a series of macroblocks. A dequantizer performs dequantization of the video data based upon a quantization threshold value. A motion-vector restoring circuit restores data for each macroblock. A direct current error detector is provided to detect erroneous macroblocks based upon the dequantized data. A motion-area error detector is provided to detect erroneous macroblocks based upon the restored motion vector data. An erroneous macroblock is replaced by a corresponding macroblock from a preceding picture. Subsequent macroblocks in a slice may also be replaced by corresponding macroblocks from a preceding picture.

Video decoder with functions to detect and process errors in encoded

An MPEG video decoder capable of preventing a buffer for storing a video stream from overflowing and/or underflowing. The video decoding apparatus decodes a coded video bit stream including a series of pictures to produce decoded pictures. The video decoding apparatus includes: a bit buffer for temporarily storing the video bit stream, a decoding circuit for receiving the video bit stream output from the bit buffer and decoding the video bit stream to produce decoded pictures, and a video bit stream control circuit for controlling an amount of the video bit stream to be supplied to the decoding circuit from the bit buffer based on an amount of data of the video bit stream stored in the bit buffer.

Video decoder capable of controlling encoded video data

Discrete cosine transform circuits suitable for inverse discrete cosine transform (IDCT) or forward discrete cosine transform (FDCT) are disclosed. An IDCT circuit includes a group of multipliers and a group of adders/subtracters. The multipliers receive plural pieces of input data which are externally supplied in parallel. Each multiplier has a cosine constant to multiply to the received input data. The adders/subtracters receive multiplication results from the multipliers and perform addition/subtraction thereon to produce output data, which is the result of inverse discrete cosine transform of the input data. An FDCT circuit includes a group of input-stage adders/subtracters, a group of multipliers, and a group of output-stage adders. The input-stage adders/subtracters perform addition/subtraction on input data which are externally supplied in parallel. Computation results of the input-stage adders/subtracters is supplied to the multipliers. The output-stage adders receive multiplication results from the multipliers and produce output data, which is the result of forward discrete cosine transform of the input data. The discrete cosine transform circuits are particularly suitable for use in MPEG video encoders/decoders.

Growing community of inventors

Osaka, Japan

Naoki Tanahashi