Japan Display Inc.

Panasonic Liquid Crystal Display Co., Ltd.

Clarion Co

Nippon Telegraph and Telephone Corporation

Hitachi Displays, Ltd.

Tachi-s Co., Ltd.

Hitachi, Ltd.

Renesas Electronics Corporation

Renesas Technology Corp.

Nec Display Solutions, Ltd.

Synaptics Japan Gk

Faurecia Clarion Electronics Co., Ltd.

Japn Display Inc.

Naoki Takada

Toshihiko Tanaka

Chihiro Tanaka

Hayato Kurasawa

Takayuki Nakanishi

Koji Ishizaki

Yasuyuki Kudo

Shota Hosaka

Mitsuru Goto

Norio Mamba

Fumitaka Gotoh

Yoshiki Kurokawa

Yuto Kakinoki

Tatsuya Wakimoto

Goro Sakamaki

Masaki Miyatake

Takao Ishikawa

Yuki Okada

Fumiaki Nakashima

Takahiro Ochiai

Hiroshi Yamaguchi

Yasuyuki Ito

Tetsuro Nakamura

Takahiko Nagasawa

Youzou Nakayasu

Kisho Yamamoto

Tsutomu Furuhashi

Akihito Akai

Takuya Eriguchi

Shinichi Komura

Masanobu Ikeda

Naruhiko Kasai

Koji Yoshida

Kenji Kono

Hiroaki Kobayashi

Hiroyuki Nitta

Yasuyuki Okada

Haruo Takeda

Kuniaki Tabata

Hirofumi Ohira

Tetsuo Machida

Hiroki Awakura

Soichiro Ohama

Shingo Takei

Masayoshi Uehara

Koji Noguchi

Kikuo Ono

Daisuke Ito

Kentaro Okuyama

Yasuyuki Teranishi

Yasuhiro Kanaya

Hiroyuki Tanaka

Junichi Maruyama

Masaki Murase

Yoshihisa Ooishi

Yukari Katayama

Nobuyuki Koganezawa

Akihiko Fujisawa

Shuuichirou Matsumoto

Yoshihiro Kotani

Takuya Nishimoto

Keita Sasanuma

Shinichi Iwasaki

Kazuo Okado

Teppei Yamada

Tsutomu Fujikake

Kazuo Noguchi

Junpei Yoshikawa

Takashi Shoji

Fumihoru Nakano

Masahiro Matsuhashi

Kenichi Ono

Akihisa Aoyama

Taiki Kasai

Ryo Kurobe

Nobuo Tsubokura

Xingle Wang

Akira Mutou

Shogo Saito

Chung-Kai Chen

Goki Toshima

Masateru Hashimoto

Yousuke Takano

Chungkai Chen

Yoshiyuki Ikehata

Masao Komada

A light sensing apparatus includes a pixel array including Thin Film Transistors (TFTs) and an interface integrated circuit including silicon transistors. The pixel array includes a plurality of pixel circuits. Each of the plurality of pixel circuits includes a light sensitive device and a detection TFT connected to the light sensitive device. The pixel array may also include a plurality of correlated double sampling (CDS) circuits each including a current source configured to provide current that biases a detection TFT in one of the pixel circuits to be configured as a source-follower. The interface integrated circuit includes at least one receiver circuit configured to receive an output of at least one of the CDS circuits. The CDS circuits may also include a bypass TFT, and the interface integrated circuit may also include a current source that provides current that biases a detection TFT in one of the pixel circuits to be configured as a source-follower when the bypass TFT is active.

Optical sensor apparatus including a pixel array having thin film transistors (TFTs)

A display device includes a substrate, a plurality of pixels provided to the substrate, and a plurality of first inorganic light emitting elements and a plurality of second inorganic light emitting elements provided to the pixels. The first inorganic light emitting elements are configured to output first light in a visible light region, and the second inorganic light emitting elements are configured to output second light in an infrared light region.

Display device

A controller server includes an assignment unit that assigns devices connected to a server to virtual machines, a usage status management unit that records correspondence between the virtual machines and devices used by the virtual machines, a warning relation management unit that records types of warnings that may occur for each of the devices during maintenance, a maintenance control unit that determines an order of an instruction for suppressing issuance of a warning that may occur for the devices during maintenance and an instruction for evacuating an affected virtual machine among the virtual machines to another server, a warning exclusion setting unit that instructs the server to exclude issuance of a warning that may occur for a device due to the maintenance, and an affected user specification evacuation unit that specifies the affected virtual machine, and evacuates the affected virtual machine from the server to the another server.

Server maintenance control device, server maintenance system, server maintenance control method, and program

According to one embodiment, a sensor device includes a panel and a control circuit. The panel includes an insulating layer, a first electrode, and a second electrode. The control circuit including a first circuit including a timing control circuit and a first amplifier, and a second circuit including a detection circuit connected to a ground line. During a first sensing drive period, the first output unit outputs a first synchronization signal, the timing control circuit outputs a second synchronization signal, the first amplifier provides the amplified second synchronization signal to each of the floating ground line and the first electrode, and the detector reads a change in a sensor signal.

Sensor device with sensor signal synchronized with a signal with reversed polarity from a signal supplied to a floating ground line

A sensor device is provided and includes electrodes each including first parts arranged in a first direction and a second part connected to the first parts, the first parts each having a first mesh shape which is formed of first metal wires, and the second part having a second mesh shape which is formed of second metal wires, wherein a longitudinal direction of the second part is the first direction, and at least one of the first mash shape and the second mash shape has an intersection portion at which two of the first metal wires or two of the second metal wires intersect.

Sensor device

According to one embodiment, a touch detection device includes first detection electrodes in a detection area, second detection electrodes in the detection area, extending to intersect the first detection electrodes, first control lines connected to the first detection electrodes, respectively, and provided in a non-detection area, and second control lines connected to the second detection electrodes, respectively, and provided in the non-detection area. The second control lines overlap the first control lines at a plurality of positions as seen in plan view, such that areas of overlapping portions in which the first control lines overlap the second control lines are substantially equalized.

Touch detection device and display device with the same

A detection device includes a plurality of first detection electrodes disposed in a matrix of rows and columns in a detection region of a substrate, at least one second detection electrode disposed in a peripheral region outside the detection region, positioned adjacent to some of the plurality of the first detection electrodes, and provided along a side of the detection region, and a coordinate calculation circuit configured to calculate a detection position of a detection target body.

Detection device having peripheral detection electrodes

According to one embodiment, a sensor device includes a panel and a control circuit. The panel includes an insulating layer, a first electrode, and a second electrode. The control circuit including a first circuit including a timing control circuit and a first amplifier, and a second circuit including a detection circuit connected to a floating ground line. During a first sensing drive period, the first output unit outputs a first synchronization signal, the timing control circuit outputs a second synchronization signal, the first amplifier provides the amplified second synchronization signal to each of the floating ground line and the first electrode, and the detector reads a change in a sensor signal.

Sensor device with timing control circuit outputting inverted polarity signal to the floating ground and sensing electrodes

According to one embodiment, a sensor device comprises a sensor configured to output a sense signal, a value the sense signal changing over time based on incident light, a first reset circuit configured to set the value of the sense signal to a reset value when the value of the sense signal exceeds a threshold, a counter configured to count a first number of times of reset by the first reset circuit, and an arithmetic operation circuit configured to calculate an amount of incident light of a certain period based on the value of the sense signal, the reset value, and the first number of times of reset.

Sensor device and sensing method

A detecting device includes a plurality of first electrodes arrayed in a first direction and a second direction intersecting the first direction in a detection region, an electrode drive circuit configured to supply a drive signal to the first electrodes, a detection circuit configured to detect a detection signal received from the first electrodes, and a coupling circuit configured to couple part of the first electrodes to the detection circuit as a detection electrode and couple the first electrodes disposed side by side with the detection electrode in at least the first direction and the second direction to the electrode drive circuit as a drive electrode in a first detection period.

Detecting device with multiplexer and display device

A proximity sensor is arranged with a first electrode input with a first signal, a second electrode input with a second signal different from the first signal, a third electrode arranged closer to the first electrode than the second electrode, and the second signal has a reverse phase of the first signal.

Proximity sensor

According to an aspect, a sensor-equipped display device includes: an array substrate; a counter substrate; a first sensor configured to detect a first detection-target object close to the counter substrate; and a second sensor configured to detect a second detection-target object close to the array substrate. A first background of the array substrate is viewed from outside the counter substrate, and a second background of the counter substrate is viewed from outside the array substrate.

Dual display device with two touch sensors

A cache usage indicator calculation apparatus () includes: a memory for reading and writing data; a cache that can be accessed more rapidly than the memory; a central processing unit configured to read and write from and to the memory and the cache and execute processing; a usage state measurement unit configured to measure a usage state of the cache used by an application () executed by the central processing unit; a performance measurement unit configured to measure a cache sensitivity and/or a cache pollutivity relating to an application (); and an indicator calculation unit configured to, based on a performance deterioration of a pre-selected plurality of applications and the usage state of the cache, calculate an indicator for the cache sensitivity and/or an indicator for the cache pollutivity of each application.

Cache usage index calculation device, cache usage index calculation method, and cache usage index calculation program

Included are at least one first semiconductor resistance element overlapping with one of the spacers and provided as the same layer as the semiconductor layer of the pixel transistors, at least one second semiconductor resistance element provided as the same layer as the semiconductor layer of the pixel transistors and not overlapping with any of the spacers, and a detection circuit detecting a force applied to the display region based on a midpoint voltage between the first semiconductor resistance element and the second semiconductor resistance element, and a resistance value of the second semiconductor resistance element is equivalent to a resistance value of the first semiconductor resistance element when no force is applied.

Performance optimization is achieved by clarifying cache usage characteristics of each application from usage conditions of physical resources (caches) in real time and automatically controlling the cache usage amount of each application. Thus, a system includes a main memory to and from which data is written and read, a level 3 cache memory which can be accessed faster than the main memory, a CPU core configured to execute processing by performing write and read to and from the memory and the cache, a usage amount measurement unit configured to measure a usage condition of a cache of each virtual machine (to) executed by the CPU core, an allocation amount calculation unit configured to calculate cache capacity to be allocated to each virtual machine (to) from the usage condition, and a control unit configured to allocate the cache capacity to each virtual machine (to).

Cache tuning device, cache tuning method, and cache tuning program

Growing community of inventors

Tokyo, Japan

Naoki Takada