Renesas Technology Corp.

Naoki Ootani

Mitsuru Sugita

Toshihiro Abe

Yoshio Kasai

A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module () outputs to a flash memory control circuit () a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit () outputs a hold signal HOLD at active 'H,' in order to inhibit a CPU () from accessing the flash memory module (). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit () outputs the hold signal HOLD at 'L' to allow the CPU () to access the flash memory module ().

Microcomputer including a flash memory and a flash memory rewrite program stored therein

Redundant circuits to are provided in correspondence to memory blocks to , respectively. Bit lines BL to BL are located across the memory blocks. Spare bit lines SBL and SBL are located across the redundant circuits to . When a memory cell failure occurs in the memory block except a predetermined memory block (for example, a boot block) and when the bit line BL corresponding to the memory cell failure is replaced with the spare bit line SBL , each of switches and is put into an on state in correspondence to the spare bit line SBL . Furthermore, each of switches and is put into the on state in correspondence to the bit line BL . As a result, the spare bit line SBL turns the redundant circuit corresponding to the memory block , to be connected to the memory block

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Tokyo, Japan

Naoki Ootani