Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Socionext Inc.

Naoki Nojiri

Yukio Nishikawa

Hideaki Hamada

Mitsuo Saitoh

Masahiro Gion

Hidetoshi Nishimura

Heiji Ikoma

Masato Maede

Koji Takemura

Shiro Usami

Yukihiro Sasagawa

Noriyuki Nagai

Ryuta Nakanishi

Koichi Taniguchi

Atsushi Doi

Fumihiko Kawai

Daisuke Matsuoka

Kenji Tanimoto

Tatsuya Tetsukawa

Mituhiro Ikeda

Michael Bi Mi

Shinji Kinuyama

Chua Tien Ping

A press-forming apparatus includes a punch, a die having an inclined surface, and a die holding plate. A blank holder has a holding surface, and a die load sensor detects a load in a pressing direction, a load in a first direction perpendicular to the pressing direction, and a load in a second direction perpendicular to the first direction. A controller calculates a normal force of the die based on the loads in the pressing direction, in the first direction, and in the second direction. The loads are detected by the die load sensor, and the controller calculates the amount of correction of clearance between the die and the blank holder based on the normal force of the die. The first driver moves the die in the pressing direction based on the amount of correction of clearance, and a second driver drives the punch in the pressing direction.

Press-forming apparatus

A machining step monitoring apparatus includes a data segmentation unit, a data length adjuster, and a determination processor. The data segmentation unit defines machining start time and machining end time of each single cycle, and segments, from a first physical quantity that temporally changes during the cycle machining in the machining machine, first measurement data indicating the first physical quantity from the machining start time to the machining end time for each single cycle. The data length adjuster generates the second measurement data by adjusting the data length of the first measurement data to match with the data length of the determination reference data indicating, as a reference, a change in the first physical quantity during the single cycle when the machining machine is normally operating. The determination processor compares the second measurement data with the determination reference data to determine whether the machining machine is normally operating.

Machining step monitoring apparatus and machining step monitoring method

A motor includes a rotor and a stator. The stator is formed by laminating a plurality of magnetic thin strips each having a plurality of teeth parts. The magnetic thin strip includes an elliptical-shaped inner diameter part formed along tip end portions of the plural teeth parts. At least one magnetic thin strip in the laminated magnetic thin strips is shifted by a given angle with respect to other magnetic thin strips in a horizontal direction, and positions of all teeth parts of the laminated magnetic thin strips correspond to one another to reduce cogging torque.

Stator and motor

An iron core including a laminate in which a plurality of nanocrystal thin strips are laminated, a board, and a fastener that fastens the laminate and the board, in which at least one of upper and lower surfaces of the laminate has a colored oxide film and an uncolored oxide film is used. Moreover, the iron core has a region of the colored oxide film wider than a region of the uncolored oxide film region is used. Furthermore, a motor uses the above-described iron core as a stator.

Iron core and motor

A method for manufacturing a thin strip component, including a processing step of processing an amorphous thin strip member into a dimension shape larger than a target shape, and a heat treating step of heat treating and contracting the amorphous thin strip member processed in the processing step to form the amorphous thin strip member into a thin strip component of the target shape. A thin strip component which is a magnetic laminate in which a plurality of plate-shaped thin strip component members of the same shape are laminated, and has a recess over an entire side surface of the magnetic laminate is used. A motor including the thin strip component, a plurality of coils disposed on the thin strip component, and a rotor disposed between the plurality of coils is used.

Thin strip component, method for manufacturing same, and motor using thin strip component

Provided is a magnetic plate laminate comprising a laminate formed by stacking a plurality of thin strips, and fastening members provided in apertures in the laminate. Also provided is a method for manufacturing a magnetic laminate wherein the thin strips are amorphous thin strips and the magnetic body laminate is subjected to heat treatment, thereby forming nano-crystalline grains in the thin strips. Also provided is a motor equipped with a stator formed by stacking a plurality of the magnetic plate laminates, a securing plate for securing the stator, and a rotor arranged in an opening in the middle of the stator.

Magnetic plate laminate, manufacturing method therefor, and motor using this laminate

An image recognition system for detecting and tracking at least an image portion associated with a predefined object from a moving picture is configured to be able to perform: an object detection processing step of detecting the object; a tracking point specification processing step of specifying a predetermined point as a tracking point; a tracking target recognition processing step of recognizing an actual tracking target based on the tracking point; a tracking processing step of tracking the tracking target; and a determination processing step of determining the type of the tracking target's behavior. The tracking point specification processing step and the determination processing step are implemented by software, while the object detection processing step, the tracking target recognition processing step, and the tracking processing step are implemented by hardware.

Image recognition system and semiconductor integrated circuit

In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes Wand Wexceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes Wand Wvia parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N, Nand two N-type low-voltage transistors N, Nfor receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

Level shift circuit

In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which constitute a current conversion circuit, supply to the signal-input transistors a current equivalent to or greater than the OFF leakage currents flowing through the signal-input transistors when they are OFF, thereby canceling the OFF leakage currents. Therefore, one of nodes which is at H level is surely fixed to a potential equal to a higher voltage supply. Thus, the level shifter surely operates with a high speed even when large OFF leakage currents flow through the signal-input transistors.

Level shifter

In an I/O circuit unit located in the periphery of a semiconductor chip, a plurality of ESD protection transistors are provided in each I/O cell. An electrode pad cell has a two-layer structure including a lower electrode pad and an upper electrode pad. The electrode pad cell is arranged so as to be present over a connection line of ESD protection transistors of an associated I/O cell. With part of the first pad portion of an adjacent electrode pad located in an end portion of the second pad portion of the electrode pad, the second pad portion can not extend further onward but the third pad portion having a smaller width than that of the second pad portion is arranged onward. Thus, destruction of the ESD protection transistors is not caused, so that an internal circuit is protected from an electrostatic discharge which comes into electrode pads.

Semiconductor device

According to the invention, in input/output circuit portions positioned around a semiconductor chip, electrode pads are arranged above each of a plurality of input/output cells arranged in a line. The width of the electrode pads is greater than the width of the input/output cells, and thus the electrode pads cannot be arranged in a single line and are instead arranged staggered in two lines. The electrode pads of one row are arranged shifted so that they do not overlap with the internal terminals of the input/output cells, but are disposed near these internal terminals. The spacing between the electrode pads is set to a distance that is at least a set distance determined by the isolation rules of the design.

In a CMOS level shifting circuit including N-channel transistors that have sources to which a digital signal is supplied, a bias voltage Vref is supplied to gates of the N-channel transistors, and the bias voltage Vref is set to be higher than a high level voltage of the digital signal and lower than a value obtained by adding a threshold voltage of the N-channel transistors to the high level voltage of the digital signal. Thus, a level shifting circuit is provided that is capable of outputting a signal having subjected to stable level conversion, even when a voltage level of a low voltage signal is lowered.

Level shifting circuit

Two NMOS transistors and two PMOS transistors are provided on a substrate. Power supply lines VDD and VSS connected to the transistors are provided in the second wiring layer. A metal line is provided in the third wiring layer, which is the uppermost wiring layer, and the pad is connected to the metal line. Even when the width of the metal line is increased so as to increase the acceptable current capacity thereof, it is possible to keep the wiring area ratio of the first wiring layer in the I/O region at a low level. Thus, it is possible to suppress the global step between the I/O region and the central region of the chip.

In a level shifter including a latch consisting of two p-channel transistors P and P , when an input signal at a terminal IN changes from H- into L-level, an n-channel transistor N turns ON, thereby dropping a potential level at a node W . However, since a p-channel transistor P is OFF, no short-circuit current flows from a high voltage supply VDD into the ground by way of the transistors P and N . On the other hand, since n- and p-channel transistors N and P are OFF, both terminals of a node W are electrically isolated. But the high voltage supply VDD pulls the node W up to a high voltage level by way of the p-channel transistors P and P and another p-channel transistor P as a resistor. Accordingly, the capacitance to be driven by the n-channel transistors N and N can be reduced, thus shortening the delay.

Growing community of inventors

Osaka, Japan

Naoki Nojiri