Fujitsu Corporation

Fujitsu Semiconductor Limited

Naoki Nishida

Sachie Tone

Hiroyuki Uno

Naoki Tanahashi

Satoru Mihara

Naoki Takahashi

Soichiro Ozawa

Masaaki Aoyama

Kunihiko Nagase

A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.

Monitor pattern of semiconductor device and method of manufacturing semiconductor device

A method for fabricating a semiconductor device with a borderless via/wiring structure includes the steps of performing borderless via etching using a resist mask to form a contact hole in an interlevel dielectric layer over a semiconductor substrate so as to expose two different metal materials of lower layer patterns in the contact hole; and performing plasma irradiation using an H2O-containing gas prior to a wet process when removing the resist mask.

Semiconductor device fabrication method

Ashing process of a resist pattern used in a semiconductor device manufacturing method is conducted by exposing the resist, the wirings, and their peripheral regions to a first atmosphere which includes a first product obtained by plasmanizing a gas containing water at a rate of more than 30 flow rate %, and placing the resist in a second atmosphere which includes a second product obtained by plasmanizing an oxygen mixed gas which contains an oxygen gas as a principal component before or after or before and after the exposing step.

Semiconductor device manufacturing method including ashing process

Growing community of inventors

Kasugai, Japan

Naoki Nishida