Nec Corporation

Naoki Nishi

Atsufumi Shibayama

Satoshi Matsushita

Sunao Torii

A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.

Data dependency detection using history table of entry number hashed from memory address

When a processor executes a memory operation instruction by means of data dependence speculative execution, a speculative execution result history table which stores history information concerning success/failure results of the speculative execution of memory operation instructions of the past is referred to and thereby whether the speculative execution will succeed or fail is predicted. In the prediction, the target address of the memory operation instruction is converted by a hash function circuit into an entry number of the speculative execution result history table (allowing the existence of aliases), and an entry of the table designated by the entry number is referred to. If the prediction is 'success', the memory operation instruction is executed in out-of-order execution speculatively (with regard to data dependence relationship between the instructions). If the prediction is 'failure', the speculative execution is canceled and the memory operation instruction is executed later in the program order non-speculatively. Whether the speculative execution of the memory operation instructions has succeeded or failed is judged by detecting the data dependence relationship between the memory operation instructions, and the speculative execution result history table is updated taking the judgment into account.

PROCESSOR, MULTIPROCESSOR SYSTEM AND METHOD FOR SPECULATIVELY EXECUTING MEMORY OPERATIONS USING MEMORY TARGET ADDRESSES OF THE MEMORY OPERATIONS TO INDEX INTO A SPECULATIVE EXECUTION RESULT HISTORY STORAGE MEANS TO PREDICT THE OUTCOME OF THE MEMORY OPERATION

An computer program instruction sequence control system to allow parallel or simultaneous execution of instructions. The system begins by loading two instructions for sequence determination. The system then checks if either instruction reads from or writes into the other instruction, if both instructions reference the same address, or if either instruction will contend with a currently executing instruction for the registers, arithmetic unit, or main memory. If no interference occurs, both instructions will be issued in parallel or simultaneously.

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Tokyo, Japan

Naoki Nishi