Sony Corporation

Naoki Nishi

Yoshiteru Kamatani

Yoshihito Higashitsutsumi

Jun Iwama

Akinori Kadota

Kazuya Yonemoto

Tetsuya Iizuka

Tetsuro Kumesawa

Yoji Takamura

Manabu Ishibashi

There is provided an imaging unit comprising at least one image sensor, a measuring instrument including at least one marker, a position computing unit, a determining unit, and an output controller, wherein the imaging unit is configured to acquire an image comprising a user and the marker, and provide the acquired image to the position computing unit, wherein the position computing unit is configured to compute a position of the marker with respect to the user based on the image provided by the imaging unit, and further provide the computed position to the determining unit, wherein the determining unit is configured to determine whether the computed position of the marker matches a retrieved measurement position, and further output the result of the determination to the output controller, and wherein the output controller is configured to provide an indication when the marker position matches the measurement position.

Information processing apparatus, information processing method, program, and measuring system

In a solid-state imaging device, bus lines are provided at both sides of an imaging area vertically to send vertical-transfer clock pulses to shunt wires disposed on or over the imaging area at both ends of the signal lines of the shunt wires. Bus lines disposed closer to a horizontal transfer register are placed at a boundary area of the imaging area and the horizontal transfer register. Since the bus lines pass through an upper layer of the boundary area, imaging performed by light receiving elements is not performed but dummy pixels having almost the same structure as the light receiving sections are disposed and vertical transfer registers are provided in the boundary area to just transfer signal charges by the vertical transfer registers with a characteristic similar to that in the imaging area to the horizontal transfer register.

Solid-state imaging device

One horizontal CCD register is provided for a plurality of vertical CCD registers. The horizontal CCD register has horizontal transfer electrodes in such a manner that transfer electrodes that are provided for each pair of vertical CCD registers adjacent to each other are independent of each other electrically. The eight transfer electrodes are supplied with eight kinds of horizontal transfer pulse signals, respectively. An operation that the horizontal CCD register consecutively outputs consecutive signal charges in the same manner as in the conventional two-phase driving method and an operation that the horizontal CCD register outputs consecutive signal charges while mixing desired ones are performed selectively by controlling the eight kinds of horizontal transfer pulse signals properly.

CCD imaging device and driving method thereof

In a charge transfer device which has many two-layered transfer electrodes,L disposed along a charge transfer direction X above a transfer channel is driven with two-phase driving pulses supplied to the transfer electrodes of the second layer, the transfer channel below the last-stage transfer electrode disposed at the last stage of the charge transfer direction X is constructed to have three-step potential, and the potential is set to be stepwise deeper from the upstream side to the downstream side in the charge transfer direction X.

Charge transfer device and solid-state image pickup device

In a charge transfer device which has many two-layered transfer electrodes, L disposed along a charge transfer direction X above a transfer channel is driven with two-phase driving pulses supplied to the transfer electrodes of the second layer, the transfer channel below the last-stage transfer electrode disposed at the last stage of the charge transfer direction X is constructed to have three-step potential, and the potential is set to be stepwise deeper from the upstream side to the downstream side in the charge transfer direction X.

A CCD shift register which is improved in the transfer efficiency with a minimal decrease in the amount of electric charge that can be handled. The CCD shift register has an array of transfer electrodes, each comprising a pair of storage and transfer gate electrodes, which are formed on a semiconductor substrate through a gate insulator. A semiconductor region under each storage gate electrode is divided into a plurality of subregions by using impurities.

CCD shift register having a plurality of storage regions and transfer

The present invention provides a CCD image sensor capable of suppressing the anomalous increase of the quantity of electric charges to be dealt with by sensor elements when a large quantity of light falls thereon without reducing the quantity of electric charges to be dealt with by vertical transfer registers and without increasing the amplitude of a pulse to be applied to the substrate when an electronic shutter operation is performed. The CCD image sensor is provided with sensor elements (1) of a HAD construction each having a hole accumulating layer (13) and arranged in vertical and horizontal rows, and heavily doped HCS regions (19) of the same type of conduction as that of the hole accumulating layers (13), formed in areas between the adjacent sensor elements of each vertical row to secure passages having a sufficient capacity for holes produced by photoelectric conversion so that the resistance against the hole current is reduced.

Charge coupled device image sensor

A solid state imager is comprised of an imager unit composed of a plurality of sensitive units arrayed in the unit of pixels in a two-dimensional manner in the horizontal and vertical directions and vertical transfer units for transferring electric charges read-out from the sensitive units in the vertical direction at every vertical column, and a horizontal transfer unit formed of charge transfer unit group (8.sub.1, 8.sub.2, 8.sub.3, . . . ) of a plurality of bits in which a clock voltage (.phi..sub.H1) is applied to a first charge transfer unit group (8.sub.1, 8.sub.3. . . ) at every other bit including the charge transfer unit (8.sub.1) of a final bit and a clock voltage (.phi..sub.H2) is applied to a second charge transfer unit group (8.sub.2, 8.sub.4, . . . ) at every other bit of the remaining bit to transfer the electric charges supplied from the image unit in the horizontal direction, wherein a cross point between a leading edge of the clock voltage (.phi..sub.H1) and a trailing edge of the clock voltage (.phi..sub.H2) is set to be a level higher than an intermediate level between peak values of the clock voltages. Thus, a so-called electric charge flooding phenomenon from the final bit (final stage) of the horizontal transfer unit to the output circuit unit can be prevented and therefore the dynamic range of the final bit can be increased relatively.

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Kanagawa, Japan

Naoki Nishi