Sony Corporation

Azbil Corporation

Naoki Nagashima

Hiroshi Takahashi

Hirofumi Sumi

Takanori Aoki

Tetsuya Kajita

Kouji Okuda

Osamu Ueda

Atsushi Seita

Seita Nashimoto

Masaki Mitsui

Taro Inami

The disclosed device easily and precisely satisfies a requested output range, and is provided with: a &#x394;&#x3a3;-modulator () which converts a digital input signal to a pulse signal; an input comparison device () which compares an input value that corresponds to the digital input signal, and a pre-set threshold value; and a thinned output control unit () which, when the result of the comparison by the input comparison device () shows that the input value is less than the threshold value, reduces the output value corresponding to the input value in accordance with the size of the difference between the input value and the threshold value, and sets the output value to 0 when the input value is 0.

Modulator and &#x394;&#x3a3;-type D/A converter

A process for fabricating a semiconductor device, which reduces the number of steps required for forming a via hole and a wiring trench in the insulating film comprised of a low dielectric-constant insulating material, resulting in a lower cost for fabrication and a shorter turn around time, is provided. A photosensitive silazane film is exposed and developed to form a hard mask on an interlayer dielectric. The hard mask defines a wiring pattern for a wiring layer and a position of a via hole. Then, a resist film is formed on the interlayer dielectric to form a resist mask having a via hole pattern, and part of a via hole is formed using the resist mask. The interlayer dielectric is subjected to anisotropic etching using the hard mask to form a wiring trench and to allow the via hole to reach the wiring layer, and the wiring layer is exposed.

Process for fabricating a semiconductor device

A method of forming wiring of a uniform film thickness using a damascene process is proposed. Tantalum nitride, copper, another copper, and another tantalum nitride, for example, all constituting conductive films of different polishing rates, are overlayed on the top layer of an insulating film in which one wiring groove and another wiring groove are formed. The film thickness of the tantalum nitride, the copper, the other copper, and the other tantalum nitride is set and formed so that the height of the surface of the tantalum nitride formed on a silicon oxide film excluding the one wiring groove matches the height of the surface of the other tantalum nitride formed on the top layer of the one wiring groove. Subsequently, polishing takes over to complete the forming process.

Method of manufacturing a semiconductor device

Disclosed is a method of fabricating a semiconductor device, including the steps of: preparing a silicon substrate on which a gate insulating film and a gate electrode composed of a polycrystalline silicon film and an insulating film are sequentially formed; forming side walls from a material having an etching selectivity to the insulating film on both sides of the gate electrode; forming a resist film on the silicon substrate so as to cover the gate electrode, and etching-back the resist film until the resist film remains on the silicon substrate except for the gate electrode to expose an upper portion of the gate electrode; selectively removing the insulating film on the gate electrode using the resist film and the side walls as a mask, and removing the resist film; and forming a refractory metal film on the silicon substrate so as to cover the gate electrode, and forming metal silicide films on the gate electrode and the silicon substrate by silicidizing, through heat-treatment, the refractory metal film with the polycrystalline silicon film of the gate electrode and with the silicon substrate.

Method of fabricating semiconductor device

A manufacturing method of a complementary MOS transistor capable of providing line width stability at the time of lithography of gate patterning and suppressing punch through of an impurity from the silicon gate electrode to the side of a substrate is proposed. A method for manufacturing a semiconductor device having a complementary MOS transistor includes the steps of forming a poly-crystalline semiconductor film (6) serving as a gate electrode on one major surface of a semiconductor substrate (3), (4) via a gate insulation film (5), forming a first solid phase diffusion source (7) containing an impurity of a first conduction type selectively on a portion of the poly-crystalline semiconductor film (6) corresponding to a first channel MOS transistor forming region (4), forming a second solid phase diffusion source (9) containing impurities of a second conduction type on an entire surface including a surface of the first solid phase diffusion source (7) and a surface of the poly-crystalline semiconductor film (6) corresponding to a second channel MOS transistor forming region (3), polishing the second solid phase diffusion source (9) by a chemical mechanical polishing technique to a position where the first solid phase diffusion source (7) is exposed, and patterning the poly-crystalline semiconductor film (6) together with the first solid phase diffusion source (7) and the second solid phase diffusion source (9) to attain a gate electrode pattern.

Method for manufacturing semiconductor device

A layer planarizing method for a semiconductor device is provided to attain excellent controllability of a polishing amount to form a uniform and flat layer without uniformity in polishing in a wafer surface. According to the method, a first layer is deposited over at least a top portion of a stepped portion formed on a surface of a body, the stepped portion covered with the first layer is covered with a second layer having a higher polishing rate than that of the first layer, and the second layer is polished until the first layer deposited on the top portion of the stepped portion is exposed.

Process for planarizing surface of a semiconductor device

A method of planarizing films in a semiconductor device, which is capable of uniformly planarizing films at a good controllability in polished amounts while keeping uniformity in polishing within a wafer surface. The method includes the steps of forming a first film on at least a step portion provided on a base body, covering the step portion with a second film containing phosphorus in an amount of from 6 to 9 wt % and higher in polishing rate than the first film, and polishing the second film to expose the first film formed on the top of the step portion.

Method of planarizing film in semiconductor device

A layer planarizing method for a semiconductor device is provided to attain excellent controllability of a polishing amount to form a uniform and flat layer on a non-uniform wafer in polishing in a wafer surface. According to the method, a first layer is deposited over at least a top portion of a stepped portion formed on a surface of a body, the stepped portion covered with the first layer is covered with a second layer having a higher polishing rate than that of the first layer, and the second layer is polished until the first layer deposited on the top portion of the stepped portion is exposed.

Transistor devices comprise a gate electrode, a channel region formed beneath the gate electrode, a source region in contact with one side of the channel region, a first conductive region formed in a semiconductor layer at the outer side of the source region and made of a metal or metal compound, a drain region formed in contact with the other side of the channel region, and a second conductive region formed in the semiconductor layer at the outer side of the drain region and consisting of a metal or a metal compound. The transistor has an SOI structure which has an improved breakdown voltage between the source region and the drain region with low sheet resistances of the source and drain regions. Methods for making the transistor devices are also described.

MOS transistor and method for making the same

The disclosure relates to a method of forming a multilayer interconnection structure. The structure is a laminated body having a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer in an ascending order. In the method, firstly, a through-hole is formed on the laminated body so as to expose a surface of the first conductive layer and two opposed surfaces of the second conductive layer. Then, the two opposed surfaces of the second conductive layer is masked with a masking film, so as not to deposit thereon a conductive material which has a strong and selective adhesion on the first and second conductive layers. Then, the conductive material is deposited on the surface of the first conductive layer by a chemical vapor deposition method so as to fill a lower portion of the through-hole with the conductive material. Then, the masking film is removed so as to expose the two opposed surfaces of the second conductive layer. Then, the conductive material is deposited on the two opposed surfaces of the second conductive layer by the chemical vapor deposition method so as to fill an upper portion of the through-hole with the conductive material, such that the through-hole is filled with the conductive material and that the first and second conductive layers are interconnected with each other.

Method of forming multilayer interconnection structure

The disclosure relates to a method of forming a multilayer interconnection structure. The structure is a laminated body having a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer in an ascending order. In the method, firstly, a through-hole is formed on the laminated body so as to expose a surface of the first conductive layer and two opposed surfaces of the second conductive layer. Then, the two opposed surfaces of the second conductive layer is masked with a masking film, so as not to deposit thereon a metal which has a strong and selective adhesion on the first and second conductive layers. Then, the metal is deposited on the surface of the first conductive layer by a chemical vapor deposition method so as to fill a lower portion of the through-hole with the metal. Then, the masking film is removed so as to expose the two opposed surfaces of the second conductive layer. Then, the metal is deposited on the two opposed surfaces of the second conductive layer by the chemical vapor deposition method so as to fill an upper portion of the through-hole with the metal, such that the through-hole is filled with the metal and that the first and second conductive layers are interconnected with each other. Even if a through-hole has a high aspect ratio, the through-hole is filled with a metal, without having a void space therein.

Growing community of inventors

Kanagawa, Japan

Naoki Nagashima