Tdk Corporation

Naoki Mukaida

Kenichi Takubo

Yukio Terasaki

Kenzo Kita

Kenzou Kita

Takashi Takahashi

Takeshi Kamono

A memory controller capable of preventing important data stored in a flash memory from being lost and maintaining the quality of a physical block. A memory controller for controlling access to a flash memory including a plurality of physical blocks, each of which includes a plurality of pages, based on a command assigned from a host system. The memory controller stores a first correspondence relationship between a logical block of a first logical region and a physical block of a first physical region in a first storage unit. The memory controller manages the first physical region in which a process of moving data saved in the physical block of the first physical region having the correspondence relationship with the logical block of the first logical region is prohibited without being based on a command for writing the data to the first logical region assigned from the host system.

Memory controller and memory system

A memory controller for preventing the storage area of a flash memory being reduced is provided. The memory controller controlling access to a flash memory based on a command provided from a host system, the memory controller includes: a processor, a RAM (random access memory), and a mask ROM (read only memory) in which a first firmware is written, wherein the memory controller is configured to: perform a search for a second firmware written in the flash memory based on the first firmware at a start-up time; and write a third firmware provided from the host system in the RAM when the second firmware is not found through the search and perform an initialization based on the third firmware written in the RAM.

A memory controller controls access to a flash memory including a plurality of physical blocks, each of which includes a plurality of pages, based on a command assigned from a host system. The memory controller allocates a physical block within the flash memory in a prescribed search range as a prescribed physical block where management information is written, writes the management information necessary for accessing the flash memory to the prescribed physical block, and operates to search for the prescribed physical block when second firmware is read from the flash memory. The writing information, including the management information, is written to the prescribed physical block in a same format regardless of a type of flash memory. Information written to pages is sequentially read at prescribed page intervals in the prescribed search range in searching for the prescribed physical block.

Memory controller for controlling multiple types of flash memories, and memory system

The object of the present invention is to efficiently perform access to a physical block corresponding to a logical block often designated by an access request. To realize it, predetermined number of pieces of logical block information each for access to a physical block corresponding to logical block, until then, designated by an access request is held. In holding the predetermined pieces of logical block information, a piece of logical block information having high priority precede a piece of logical block information having low priority in priority order. In management of the priority order, priority of a piece of logical block information corresponding to a logical block often designated by an access request becomes high. When an access request is received, if logical block information corresponding to the logical block designated by the access request is held, access to the physical block corresponding to the designated logical block is performed based on the held logical block information.

Memory controller, flash memory system with memory controller, and method of controlling flash memory

The memory controller updates a count number based on a new assignment of a logical block to a physical block, and writes count information in the physical block to which the logical block is newly assigned. The count information is defined by the count number. The memory controller decides, based on the count number and the count information stored in each physical block, whether or not to transfer stored data in a physical block to another physical block.

Memory controller, flash memory system with memory controller, and control method of flash memory

In the control of the number of program-erase cycles, physical blocks (PBs) are divided into plural groups on a basis of the number of program-erase cycles and a search for a free PB is performed in the groups when assigning a logical block (LB) to the free PB. In the search, a free PB among a group covering a small number of program-erase cycles precedes that among a group covering a large number of program-erase cycles. Further, when searching out a free PB in the search, data stored in a PB (source PB) included in a group covering a smaller number of program-erase cycles than that covered by a group including the free PB searched out are transferred to the free PB if there is the source PB. The source PB is a PB to which a LB is assigned earliest among a group including it.

Memory controller, memory system with memory controller, and method of controlling flash memory

In the control of the number of program-erase cycles, when assigning a logical block (LB) to a physical block (PB), the number of program-erase cycles of a first PB and that of a second PB are compared, which first PB is a free PB of which the number of program-erase cycles is the smallest among that of free PBs, which second PB is a PB earliest assigned a LB among PBs each assigned a LB. As a result, in a case where the number of program-erase cycles of the first PB is larger by a predetermined value or more than that of the second PB, data stored in the second PB are transferred to a free PB of which the number of program-erase cycles is the largest among free PBs, and then the LB is assigned to the second PB.

Access to flash memories is controlled so that efficiency of data writing and effective utilization of storage area go together. In the access control, priority order, for physical blocks each storing effective data, is managed so that a position of a physical block in the assignment order becomes higher according as assignment of a logical block to the physical block is performed more recently. When assigning a logical block to a free physical block, a determination is made whether a position of a previous physical block is higher than a predetermined position in the priority order. The previous physical block is a physical block, then, corresponding to the same logical block as the free physical block. When the determination is negative, effective data stored in the previous physical block is transferred to the free physical block.

A flash memory stores a boot program of a host system and its backup program. A memory controller determines whether or not the boot program is stored properly in the flash memory when the host system is to be activated. The memory controller reads out the boot program in a case where the boot program is stored properly, and reads out the backup program in a case where the boot program is not stored properly. Then, the memory controller supplies the read-out boot program or backup program to the host system. This makes it possible to avoid a situation that the host system cannot be activated due to the boot program not being able to be executed.

Memory controller, flash memory system, and control method of flash memory

Chronological identification information is composed of a plurality of cyclic numbers with priorities. For generating new chronological identification information, the chronological relation is compared in order from cyclic numbers with the highest priority to extract the newest chronological identification information in the chronological relation; when the newest chronological identification information in the chronological relation is extracted, a cyclic number with a priority as a comparison target in the extraction of the extracted chronological identification information is determined to be a cyclic number with the priority in the newly generated chronological identification information. When the cyclic numbers with a priority compared as comparison targets in the chronological identification information all are equal, no further extraction is carried out and the cyclic number subsequent to the cyclic numbers is determined to be a cyclic number with the priority in the newly generated chronological identification information.

Chronological identification in flash memory using cyclic numbers

A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target page designated by a host address is possible, and write means responsive to an affirmative determination by the decision means for writing user data to the target page without performing an inter-block data transfer. Thus, a series of data write operations for completing data writing can be performed at high speed because the frequency of inter-block data transfers is low.

Memory controller, flash memory system having memory controller and method for controlling flash memory device

There is disclosed a controller included in a flash memory system attachable to a memory interface of a host system. If a block in which new data is written and a block in which old data is written are present simultaneously, the controller determines in which block the newest data is written, based on version identifier stored in a redundant area of a flash memory. Specifically, the controller has an access control function for controlling access to the flash memory, an address managing function for managing correspondence between a logical block address supplied from the host system and a physical block address in the flash memory, a version identifier setting function for writing version identifier in the redundant area of the flash memory, and a version identifying function for identifying a block in which newest data corresponding to a same logical block address is written based on the version identifier.

Memory controller, flash memory system, and method for recording data on flash memory

A memory controller which can perform a series of data write operation to a flash memory device fast is disclosed. The memory controller according to an embodiment of the present invention is the memory controller for accessing a memory having a plurality of physical blocks based on a host address provided from a host computer. The memory controller has means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to different groups, the virtual blocks can be divided into at least a first class and a second class, and means for assigning adjacent host addresses into different physical blocks belonging to the same virtual block of the first class and assigning adjacent host addresses into the same physical blocks belonging to the same virtual block of the second class.

Memory controller, flash memory system employing memory controller and method for controlling flash memory device

A memory controller which can perform a series of data write operation to a flash memory device fast is disclosed. The memory controller according to the present invention is the memory controller for accessing a memory having a plurality of physical blocks based on a host address provided from a host computer. The memory controller has means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to different groups, the virtual blocks can be divided into at least a first class and a second class, and means for assigning adjacent host addresses into different physical blocks belonging to the same virtual block of the first class and assigning adjacent host addresses into the same physical blocks belonging to the same virtual block of the second class.

An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed. A memory controller includes means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to a different group, and means for assigning adjacent host addresses to different physical blocks belonging to the same virtual block. Thus, when a host computer issues a request to access the plurality of successive host addresses, the physical blocks to be accessed are different physical blocks. Since the physical blocks to be accessed can therefore operate independently, a series of operations can be performed in parallel.

Growing community of inventors

Tokyo, Japan

Naoki Mukaida