Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Microcomputer System, Ltd.

Naoki Mitsuishi

Kiyoshi Matsubara

Shiro Baba

Tsutomu Hayashi

Hiromi Nagayama

Yukihide Hayakawa

Toshimasa Kihara

Hiroshi Saito

Yoshiyuki Ozawa

Koichi Hashimura

Yoh Takamori

Hiroyuki Kobayashi

Kenichi Ishibashi

Hisashi Kajiwara

Mitsumasa Satoh

Masahiko Takeshima

Hiromasa Yamagata

Takahiro Okubo

Kenji Takechi

Shinichi Shibahara

Atsushi Hirose

An apparatus and method for selecting whether a central processing unit (CPU) performs instruction reading in units of 16 bits (a first word length) or in units of 32 bits (a second word length). Depending on whether instruction reading is performed in units of 16 bits or 32 bits, increment values (+2 and +4) by which a program counter (PC) is incremented are switched. Data reading or writing is performed in units of a given data length irrespective of the selecting unit. When the CPU issues a request for instruction reading in units of 16 bits or 32 bits or for data reading or writing, a bus control unit performs reading or writing a predetermined number of times according to a bus width designated for a resource located at an address specified in the request.

Data processor with selectable word length

It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

Data transfer device, semiconductor integrated circuit, and microcomputer

A microcomputer is provided with a data-transfer unit such as a DMA (direct memory access) controller for controlling a transfer of data through an external bus. Used in an access to an external device controlled by the data-transfer unit, a bus-interface means of the microcomputer includes a buffer-register means which can be specified as either a source location or a destination location of a data transfer. Thus, an internal-bus master such as a CPU employed in the microcomputer is capable of reading out information such as a packet command from the buffer-register means at a high speed through an internal bus without using the external bus and, hence, capable of carrying out an operation reflecting a transfer control condition specified by the packet command.

Microcomputer and microcomputer system

There is provided a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility. Register designating information for designating a register is divided in two portions. The two portions are arranged in separate basic units on the basic units of an instruction code. When one instruction code is made ignorable and the ignorable instruction code is ignored, a control unit (CONT) executes register selecting operation by implicitly assuming predetermined register designating information. Thereby, when only a general purpose register (existing general purpose register) capable of being designated implicitly is used, the ignorable instruction code can be ignored and accordingly, the instruction codes are not increased. When an at least conventionally equivalent general purpose register is used, a conventionally equivalent instruction code may be used. By preventing the instruction codes from increasing, processing speed is not reduced.

Data processing apparatus

Two up-counters and two down-counters having a time difference corresponding to a dead time are provided to realize an up-down symmetric count, such that the up-counters and the down-counters are made to count the lower limit and the upper limit (a 1/2 period+the dead time), the up-counter for counting a relatively large value and the down-counter for counting a relatively large value are made to contact at the upper limit, the up-counter for counting a relatively small value and the down-counter for counting a relatively small value are made to intersect at a count value corresponding to the 1/2 period, the up-counter for counting the relatively large value and the down-counter for counting the relatively large value are made to intersect at the count value corresponding to the dead time, and the up-counter for counting the relatively small value and the down-counter for counting the relatively small value are made to contact at the lower limit.

Microprocessor having timer circuit generating complementary

The invention provides a semiconductor integrated circuit device, which minimizes an increase in the physical and logical size, allows data transfers invoked by a large number of interrupts, and improves the processing efficiency. This semiconductor integrated circuit device is applied to a single chip microcomputer and includes function blocks such as CPU, data transfer controller DTC, ROM, RAMI, RAMP, timer, pulse output circuit, serial communication interface SCI, A/D converter, IOP0-11, interrupt controller, and bus controller BSC. The internal address bus IAB and the internal data bus IDB are connected to CPU, ROM, RAMI and BSC. The internal address bus PAB and the internal data bus PDB are connected to BSC, RAMP, timer, pulse output circuit, SCI, A/D converter, interrupt controller, and IOP0-11. Further, PDB is connected to DTC.

Semiconductor integrated circuit device with a central processing unit,

Semiconductor integrated circuit device

A semiconductor integrated circuit comprising a clock pulse generator, peripheral function blocks and bus master modules. The peripheral function blocks are commonly supplied with a first system clock signal of a constant frequency generated on the basis of the output from the clock pulse generator. The bus master modules are fed with a second system clock signal generated on the basis of the pulse generator output. The frequency of the second system clock signal is variable and lower than that of the first system clock signal. The function blocks supplied with the first system clock signal are connected to a data bus separate from the one connected to the function blocks fed with the second system clock signal.

Integrated circuit having function blocks operating in response to clock

Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in a CPU 1 of 8 bits so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU. This register can be used in its entirety, dividing it in half or by dividing it in quarters. As a result, the register can be excellently used on a software or hardware to reduce the logical and physical scales of the CPU. In respect of the latch of the address data using the register wholly or partially, moreover, the address space to be linearly used can be easily expanded.

Single-chip microcomputer having an expandable address area

In a semiconductor integrated circuit device having an A/D converter incorporated therein, a plurality of input channels are provided and input analog signals supplied therefrom are respectively held by a plurality of sample-to-hold circuits. The analog signals are simultaneously sampled by using such a pipeline operation that a first sampling is performed so that an analog signal held by the first sampling is A/D-converted and a second sampling is performed so that an analog signal held by the second sampling is A/D-converted, and the plurality of sample-to-hold circuits.

Semiconductor integrated circuit device and control system

Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in an 8-bit CPU (1) so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU. This register can be used in its entirety, by dividing it in half or by dividing it in quarters. As a result, the register can be used on software or hardware to reduce the logical and physical scales of the CPU. In respect of the latch of the address data using the register wholly or partially, moreover, the address space to be linearly used can be easily expanded.

A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address register with a bit number larger than the address bit number of a low-order CPU. The data information has its byte/word size specified by the size bit of an operation code. The utilization of the data information of a long word size is specified by either the prefix code or the operation code to which is newly added the same bit number as that of the low-order CPU. For the data information of the byte size, the high-/low-orders of the byte size register to be utilized are specified by predetermined 1 bit of a register specifying field. For the data information of the word size, the high-/low-orders of the word size register are specified by the predetermined 1 bit of that data information.

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Kodaira, Japan

Naoki Mitsuishi