Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Nec Corporation

Kioxia Corporation

Jfe Steel Corporation

Naoki Matsunaga

Kenji Sera

Shigeru Endo

Kazukuni Hase

Katsuyuki Ichimiya

Shigeki Kitsuya

Kenji Hayashi

Mitsuasa Takahashi

Yusuke Terazawa

Masayuki Horie

Teruhisa Kinugawa

According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Non-volatile semiconductor storage device

A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

Multi-chip package and memory system

A high toughness and high tensile strength thick steel plate has a plate thickness of 100 mm or more, wherein a reduction of area in a center of the plate thickness by tension in a plate thickness direction is 40% or more. Thus, a high tensile strength thick steel plate with excellent strength and toughness in a center of the plate thickness can be obtained with no need for a larger production line, even in the case of producing a high strength thick steel plate for which the addition amount of alloying element needs to be increased.

High toughness and high tensile strength thick steel plate and production method therefor

A thick, high-toughness high-strength steel plate has excellent strength and toughness in the central area through the plate thickness. The thick steel plate has a specific chemical composition and includes a microstructure having, throughout an entire region in the plate thickness direction, an average prior austenite grain size of not more than 50 &#x3bc;m and a martensite and/or bainite phase area fraction of not less than 80%. A continuously cast slab having the specific chemical composition is heated to 1200&#xb0; C. to 1350&#xb0; C., hot worked with a strain rate of not more than 3/s and a cumulative working reduction of not less than 15%, and thereafter hot rolled and heat treated.

Thick, tough, high tensile strength steel plate and production method therefor

A memory device includes a substrate, a plurality of nonvolatile memory chips disposed on the substrate, and a memory controller disposed on the substrate. The memory chips may be disposed on the same side or the opposite side of the substrate as the memory controller. The memory controller controls each of the nonvolatile memory chips based on a firmware, where the firmware is written in a nonvolatile memory chip positioned at a location farthest from the memory controller. A write system may perform writing using a binary or single level cell (SLC) recording system in memory chips located closest to the memory controller and a multi-value or multi-level cell (MLC) recording system in memory chips located farthest from the memory controller. A weighting factor may be assigned for each of the nonvolatile memory chips based on the distance from the memory controller.

Memory system in which data is written to memory chips based on a distance from a memory controller

Growing community of inventors

Tokyo, Japan

Naoki Matsunaga