Fujitsu Corporation

Naoki Maezawa

Hiroaki Watanabe

Chikahiro Deguchi

Yoshiki Okumura

Yutaka Sekino

Hideyuki Negi

A semiconductor integrated circuit includes a combinational circuit to output a state value and a parity value, a first parity check circuit to perform a parity check based on the state value and the parity value stored in a first FF circuit and output a first parity error, a second parity check circuit to perform a parity check based on the state value and the parity value stored in a second FF circuit and output a second parity error, and a selector to, when the first parity error is not output but the second parity error is output, output the state value in the first FF circuit to the combinational circuit, and when the first parity error is output but the second parity error is not output, output the state value in the second FF circuit to the combinational circuit.

Semiconductor integrated circuit and method of processing in semiconductor integrated circuit

A configuration method performs a configuration of a FPGA circuit by setting configuration data from a configuration circuit to the FPGA circuit. The method counts, within the FPGA circuit, a number of times a configuration of the FPGA circuit fails. The method adjusts, within the FPGA circuit, the configuration data at a time when the configuration failed if the counted number exceeds an upper limit value, and re-executes the configuration based on the adjusted configuration data. The method sets the configuration data in which the configuration is succeeded from the FPGA circuit to the configuration circuit when the configuration is successful.

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Toyohashi, Japan

Naoki Maezawa