Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Naoki Kusunoki

Nobutoshi Aoki

Toshiyuki Enda

Riichiro Shirota

Hiroyoshi Tanimoto

Fumitaka Arai

Hideaki Aochi

Masaru Kito

Hiroshi Watanabe

Ryota Katsumata

Masaru Kidoh

Ichiro Mizushima

Makoto Mizukami

Akihiro Nitayama

Kiyotaka Miyano

Takayuki Miyazaki

Masaki Kondo

Hiroki Tokuhira

Takamitsu Ishihara

Sanae Ito

Hirotaka Amakawa

A storage device includes a first group of wirings extending in a first direction, a second group of wirings extending in a second direction, and memory cells between the first and second groups, each including a variable resistance element and a selection element becoming conductive when a voltage greater than a threshold is applied. Va applied across a first cell to be selected satisfies Va&#x3e;Vd&#x3e;Vb and Va&#x3e;Vd&#x3e;Vc. A first wiring of the first group and a second wiring of the second group are connected to the first cell. A third wiring of the first group and a fourth wiring of the second group are adjacent to the first wiring and the second wiring. Vb, Vc, and Vd are applied across a second cell between the first and fourth wirings, a third cell between the second and third wirings, and a fourth cell between the third and fourth wirings.

Storage device

A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

Nonvolatile semiconductor memory device

A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

Non-volatile semiconductor memory and method for controlling a non-volatile semiconductor memory

A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.

A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

Semiconductor memory device

A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.

Method of fabricating a semiconductor memory device

Plural boundary points are generated on a string on the surface of a material and a first length of a line segment between the boundary points is obtained. Then, the displacement of the boundary point according to a process model and the boundary point is moved by the displacement. A second length of the line segment between the boundary points after the boundary point is moved is found. When the second length is greater than a value obtained by multiplying the first length by a first factor exceeding 1, a new boundary point is added to the line segment whereas when the second length is smaller than a value obtained by multiplying the first length by a second factor less than 1, one of the boundary points of the line segment is eliminated.

Method of simulation of production process of semiconductor device and simulator thereof

A simulation method simulates a self-aligned silicide (SALICIDE) process according to heat treatment temperature and changes in the composition of a silicide film during first and second heat treatments. The simulation method separately simulates silicide reactions in the first and second heat treatments according to species (metal or silicon) diffusing through a silicide, to thereby improve the accuracy of simulations.

Semiconductor device simulation method, semiconductor device simulator, computer program for semiconductor device simulation, and method of manufacturing the semiconductor device

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Fuchu, Japan

Naoki Kusunoki