Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Sakai Display Products Corporation

Sharp Kabushiki Kaisha Corporation

Matsushita Electronics Corporation

Naoki Kotani

Shinji Takeoka

Gen Okazaki

Akio Sebe

Junji Hirase

Kazuhiko Aida

Tokuhiko Tamaki

Kenichi Mukai

Keiichiro Shimizu

Chikanori Tsukamura

Kazunori Yamamoto

Tatsuya Tezuka

Kenta Takeuchi

Taiki Hayai

Kimio Takahashi

Provided are: a display panel whereby a frame can be narrowed, while ensuring conduction between substrates; a display device; and a method for manufacturing the display panel. The display panel is provided with: a first substrate having a surface, on which an electrode layer is formed; a second substrate having a surface, on which a wiring path for supplying the electrode layer with signals is formed; and a sealing section that defines a space sealed between the first substrate surface and the second substrate surface, which are facing each other. The display panel is also provided with a columnar section that electrically connects the electrode layer to the wiring path. The columnar section is formed at a position in contact with the sealing section.

Display panel, display device, and method for manufacturing display panel

Provided is a liquid crystal display apparatus such that a liquid material for an alignment film can be prevented from entering a region for forming a sealing member so that the peeling of the sealing member caused by the deterioration of adhesion between the sealing member and a substrate can be prevented and a narrow frame can be attained. A display panel includes a rectangular-shaped TFT substrate and CF substrate bonded together with a sealing member formed at a periphery thereof, a liquid crystal layer provided at a region surrounded by the sealing member between the two substrates to form a display region, and an groove and protrusion part provided between the display region and the sealing member having a groove formed along a circumferential direction in a region between the display region and the sealing member, the groove and protrusion part having wave-like shape in a plan view.

Liquid crystal display apparatus

A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

Semiconductor device

A semiconductor device includes a plurality of first cells having a first cell height, and a plurality of second cells having a second cell height. Each of the first cells has a first MIS transistor of a first conductivity type, and a substrate contact region of a second conductivity type. Each of the second cells has a second MIS transistor of the first conductivity type, a power supply region of the first conductivity type, and a first extended region of the first conductivity type that is silicidated at a surface thereof. The first cell height is greater than the second cell height.

Semiconductor device and design method thereof

A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.

Semiconductor device including a SRAM section and a logic circuit section

A substrate for a display having, on a surface thereof, a sealing compound disposed along a periphery of the substrate spaced at a predetermined interval from an outer edge of a display part to which an oriented film is applied; and a convex portion or/and a concave portion, for preventing the applied oriented film from spreading to the sealing compound, provided between the sealing compound and the outer edge of the display part. The convex portion has a configuration of a bank continuous or uncontinuous, whereas the concave portion is formed as a plurality of independent portions arranged side by side or dotted between the outer edge of the display part and the sealing compound.

Board for display device and display device

The distance between a substrate contact portion and an active region in a p-type MIS transistor is greater than the distance between a substrate contact portion and an active region in an n-type MIS transistor. Alternatively, the length of a protruding part of a gate electrode of the p-type MIS transistor that protrudes from the p-type MIS transistor's active region toward the p-type MIS transistor's substrate contact portion is shorter than the length of a protruding part of a gate electrode of the n-type MIS transistor that protrudes from the n-type MIS transistor's active region toward the n-type MIS transistor's substrate contact portion. Alternatively, a part of the p-type MIS transistor's substrate contact portion that is located opposite the p-type MIS transistor's gate electrode has a lower impurity concentration than the other part thereof. Alternatively, a protective film is formed only on the protruding part of the p-type MIS transistor's gate electrode that protrudes from the p-type MIS transistor's active region toward the p-type MIS transistor's substrate contact portion.

Semiconductor device and method for fabricating the same

Both a compressive-stress-applying insulating film and a tensile-stress-applying insulating film cover an N-type MIS transistor formed at an SRAM access region of a semiconductor substrate. On the other hand, a tensile-stress-applying insulating film covers an N-type MIS transistor formed at an SRAM drive region of the semiconductor substrate.

SRAM semiconductor device with a compressive stress-inducing insulating film and a tensile stress-inducing insulating film

Method of manufacturing a semiconductor device including a SRAM section and a logic circuit section

In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS are covered with a layered film including a tensile stress applying film and a compressive stress applying film.

Semiconductor device comprising a stress applying insulating film

In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS are covered with an insulating film which applies lower stress than the stresses applied by the above-described two films.

A MIS transistor includes a gate electrode portion, insulating sidewalls formed on side surfaces of the gate electrode portion, source/drain regions and a stress film formed so as to cover the gate electrode portion and the source/drain regions. A height of an upper surface of the gate electrode portion is smaller than a height of an upper edge of each of the insulating sidewalls. A thickness of first part of the stress film located on the gate electrode portion is larger than a thickness of second part of the stress film located on the source/drain regions.

A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region. The gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.

Growing community of inventors

Hyogo, Japan

Naoki Kotani