Mitsubishi Electric Corporation

Naoki Kosaka

Ko Kanaya

Shinichi Miwa

Atsushi Okamura

Yoshihiro Tsukahara

Ayumi Fuchida

Kenichiro Chomei

Kazuya Yamamoto

Masaaki Shimada

Koji Yamanaka

Naoki Nakamura

Miyo Miyashita

Yoshinobu Sasaki

Hiroshi Otsuka

Toshiyuki Oishi

Go Sakaino

Kenichi Horiguchi

Katsuya Kato

Yutaro Yamaguchi

Hiroaki Maehara

Hirotaka Amasuga

Shohei Imai

Tadashi Takase

Eri Fukuda

Kou Kanaya

Shigeru Fujiwara

A semiconductor laser device disclosed in this application is characterized; wherein one of the reflective surface and the secondary reflective surface is constituted by a dielectric multi-layer film that is formed on a PD chip for measuring a light quantity of the laser light; and wherein an inclination angle of the reflective surface is set to a value obtained by subtraction of a value that is less than an inclination angle of beam center, from 45 degrees, while an inclination angle of the secondary reflective surface is set to a value obtained by subtraction of a value that is more than the inclination angle of beam center, from 45 degrees.

Semiconductor laser device

A semiconductor laser device comprises a stem serving as a base; a laser diode LD submount having surface electrodes arranged thereon and joined to the surface of the stem; an LD chip joined to the surface electrode and connected with the surface electrode; and leads fixed in through holes formed in the stem by means of sealing parts and electrically connected to the surface electrodes via embedded layers in via holes formed in the LD submount, wherein grooves are formed in portions of the sealing parts or in portions of the LD submount around the connections between the leads and the embedded layers, to obtain a good modulated light waveform.

In the present invention, in addition to arranging a plurality of amplifying elements in a staggered manner, signal path lengths from an input-side divider to gate pads of the plurality of amplifying elements are equalized, and signal path lengths from drain pads of the plurality of amplifying elements to an output-side combiner are equalized.

Amplifier

A power amplifier includes: a plurality of FET cells connected in parallel to each other; a plurality of first resistors connected between gate terminals of the plurality of FET cells and grounding terminals respectively; a plurality of second resistors having one ends connected to the gate terminals of the plurality of FET cells respectively and other ends connected to each other; a plurality of capacitors connected in parallel to the plurality of second resistors respectively; and a third resistor connected between a connection point of the other ends of the plurality of second resistors and a power supply terminal, wherein the first resistors have temperature coefficients of resistance greater than those of the second and third resistors and are arranged closer to the corresponding FET cells than the third resistor.

Power amplifier including a plurality of FET cells connected in parallel

An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.

Amplifier package with multiple drain bonding wires

A power amplifier includes a semiconductor substrate including transistor cells, a drain electrode for the transistor cells located on the semiconductor substrate, a drain pad located on the semiconductor substrate and connected to the drain electrode, an ion-implanted resistance located in the semiconductor substrate and extending along and in contact with the drain pad, a floating electrode located on the semiconductor substrate and in contact with the ion-implanted resistance, and an output matching circuit located outside the semiconductor substrate. The power amplifier further includes a wire connecting the drain pad to the output matching circuit.

Power amplifier

A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.

Transistor characteristic calculation apparatus using large signal equivalent circuit model

A semiconductor circuit substrate includes a transistor-forming substrate and a circuit-forming substrate. The transistor-forming substrate is a GaN substrate and has a Bipolar Junction Transistor (BJT) located in its top surface. The bottom surface of the transistor-forming substrate is flat and has contact regions. The circuit-forming substrate is a material other than a compound semiconductor and has no semiconductor active elements. The circuit-forming substrate has a flat top surface, contact regions buried in and exposed at the top surface, and passive circuits. The transistor-forming substrate and the circuit-forming substrate are directly bonded together without any intervening film, such as an insulating film.

Semiconductor device and semiconductor circuit substrate

In making an airbridge structure, a second resist layer is applied over a first resist layer. The resist layers are exposed and developed to have a predetermined width W. A third resist layer is applied. The third resist layer is also exposed and developed to have a predetermined width W. An airbridge-forming material layer is applied to the layer stack structure consisting of the first, second, and third resist layers, forming an airbridge. The resist layers are removed, completing the manufacture of the airbridge, which has a stepped cross section.

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Tokyo, Japan

Naoki Kosaka