Kabushiki Kaisha Toshiba

International Business Machines Corporation

Toshiba America Electronic Components, Inc.

Naoki Kiryu

Louis Bernard Bushard

Nathan Paul Chelstrom

David John Krolak

Tilman Gloekler

Christian Habermann

Johannes Koesters

Joachim Kneisel

Mack Wayne Riley

Yukihiro Urakawa

Akihiko Fukui

A semiconductor device includes a BIST circuit configured to detect a defective bit in a DRAM connected to the semiconductor device, and retrieve an address of the detected defective bit, a non-volatile eFuse macro configured to retain the address of the defective bit in the DRAM, the defective bit being detected by the BIST circuit, and a repair register configured to store data for the address of the defective bit. The semiconductor device also includes an address controller configured to, based on the address retained in the eFuse macro, perform control to use the repair register during writing or reading of data to or from the address of the defective bit.

Semiconductor device, semiconductor package and memory repair method

A data transfer circuit includes: an asynchronous memory to which transfer data is written from a first clock domain with a first clock and from which the written transfer data is read to a second clock domain with a second clock; a scan flip-flop whose input terminal is connected to a first position located on a data path, of the transfer data, from the asynchronous memory to the second clock domain, and whose output terminal is connected to a second position located on a data path, of the transfer data, from the asynchronous memory to the first position; and a clock selector which selects a clock to drive the scan flip-flop from the first clock and the second clock.

Data transfer circuit

A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.

Method and apparatus for testing a ring of non-scan latches with logic built-in self-test

Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) by determining weighting and/or seed values to be used in generating pseudorandom test bit patterns for each channel to optimize fault coverage. In one embodiment, a method includes generating a pseudorandom sequence of bits, applying a weighting value to the sequence, propagating the weighted sequence through one or more levels of logic, and capturing the resulting data. Metrics are then applied to the captured data to determine the suitability or optimality of the weighting value, and an optimal weighting value is selected. This may be performed for a plurality of trial values for each of a number of channels to obtain a set of weighting values for the different LBIST channels. The method may also include determining a seed value for the pseudorandom bit pattern generator.

Systems and methods for improved fault coverage of LBIST testing

Systems and methods for performing logic built-in-self-tests (LBISTs) where data comparisons are performed in the MISR. In one embodiment, a STUMPS-type LBIST architecture includes scan chains interposed between portions of the functional logic of the logic circuit. Test bit patterns are scanned into the scan chains, propagated through the functional logic, and captured in scan chains following the functional logic. The bits are scanned out of the scan chains into a self-compare MISR that creates a signature from the computed bit patterns and then compares the signature of the computed bit patterns with an expected signature, giving a pass/fail result. This single bit result reduces the bandwidth required to communicate the result(s) of the LBIST testing to the test equipment. As a result, a larger number of devices can be tested by a given piece of test equipment.

Multi-test method for using compare MISR

Systems and methods for performing logic built-in-self-tests (LBISTS) in digital circuits. In one embodiment, the operation of LBIST circuitry is suspended at the end of each test cycle so that the bit patterns generated by the functional logic of the device under test can be examined to determine if any errors occurred during the test cycle. Pseudorandom bit patterns are scanned into the scan chains interposed between portions of the functional logic circuit and then propagated through the functional logic. The resulting bit patterns are captured in scan chains following the functional logic and then scanned out of the scan chains. The bit patterns are processed and compared to corresponding data generated by a parallel LBIST system in a device that is known to operate properly. The LBIST test cycles are then halted if there are errors in the generated bit patterns or resumed if there are no errors.

Systems and methods for circuit testing using LBIST

Systems and methods for controlling the execution of LBIST test cycles to allow identification of errors in bit patterns produced by the functional logic of a device under test. In one embodiment, an LBIST controller enables continuous execution of LBIST test cycles (including functional and scan shift phases) prior to a test cycle in which an error arises. In the test cycle in which the error arises, the controller allows execution of the functional phase, but not the following scan shift phase. The computed bit patterns captured in the scan chains are thereby retained in the scan chains, rather than being accumulated into a single MISR signature value. The computed bit patterns can then be retrieved from the scan chains (e.g., via a JTAG chain) and examined to determine the exact location of the error.

Systems and methods for identifying errors in LBIST testing

Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed to determine whether any of the processor cores is malfunctioning. If none of the processor cores malfunctions, the processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor is fully functional. If one or more processor cores malfunctions, these processor cores are isolated and the remaining processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor operates properly with reduced functionality.

Systems and methods for LBIST testing using isolatable scan chains

The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

Apparatus for accelerating through-the-pins LBIST simulation

Systems and methods for performing logic built-in self-tests (LBISTs) to detect 'at-speed' errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target logic of the digital circuit and captured in scan chains at a normal operating speed to produce a first output bit pattern. This is repeated with the first input bit pattern at a lower test speed to produce a second output bit pattern. Differences between the first and second output bit patterns are then detected to determine whether operation of the digital circuit at the normal operating speed causes errors that are not generated at the lower test speed.

Systems and methods for diagnosing rate dependent errors using LBIST

Systems and methods for performing logic tests in digital circuits with means for segmentation and output of data through limited I/O ports. In one embodiment, a system includes test circuitry coupled to target logic under test, where the test circuitry is configured to perform logic tests on the target logic using input data and thereby generate signature data. The system includes a first number of I/O ports that are shared for input and output and alternately convey the input data to the test circuitry and output the signature data generated by the test circuitry. The signature data includes a second number of bits greater than the number of I/O ports. The test circuitry is configured in a first mode to successively output multiple segments of the signature data through the I/O ports, where each segment has a number of bits no greater than the number of I/O ports.

Systems and methods for providing output data in an LBIST system having a limited number of output ports

The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

Method and apparatus for accelerating through-the pins LBIST simulation

Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where the LBIST circuitry is configured to propagate data through different portions of the functional logic of the circuits at different times. In one embodiment, a logic circuit incorporates LBIST components including a set of scan chains interposed between portions of the functional logic. Pseudorandom bit patterns are scanned into the scan chains so that they can be propagated through the functional logic following the scan chains. The resulting bit patterns are captured in scan chains following the functional logic and then scanned out of these scan chains. An LBIST controller causes functional operations in different portions of the functional logic to be performed at different times during a functional phase of a test cycle. The functional operations may be performed at a normal operating speed, while scan shift operations may be performed at a lower speed.

Systems and methods for LBIST testing using multiple functional subphases

Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where scan shift operations of the LBIST circuitry are performed at reduced rates. In one embodiment, a base clock signal is gated before being provided to LBIST circuitry. The clock signal is gated to produce an effective clock rate that is reduced in one or more steps from a first rate that is used in a functional phase of LBIST testing to a reduced rate that is used in a scan shift phase. The effective clock rate is stepped back up at the end of the scan shift phase to the first rate which is used in the following functional phase.

Growing community of inventors

Austin, TX, United States of America

Naoki Kiryu