Kawasaki Steel Corporation

Kawasaki Microelectronics, Inc.

Naoki Kanazawa

Masato Yoneda

Hiroshi Sasama

Ryuichi Hata

Masahiro Konishi

Hideaki Iwasaki

Hajime Kinugasa

A content addressable memory includes a plurality of word memories which respectively have assigned addresses, and each outputs a match/mismatch signal representing storage or no storage of a data item matching search data in a search mode, a priority encoder which output addresses of word memories which output the match signals in the search mode in predetermined fixed priority order, a first prior word-memory setting section for setting a first prior word memory, and a priority changing part which masks the match signals output from upper-positional word memories of the word memories, which correspond to word memories having upper positions compared with the first prior word memory in the fixed priority order in the priority encoder, and transmits signals representing that the word memories having the upper positions output no match signals to the priority encoder.

Content addressable memory capable of changing priority in priority encoder

A signal detection circuit detects the presence or absence of signals having the same logic in a plurality of arranged signal lines, can be used as a circuit suitable for multi-hit detection in a content addressable memory. The signal detection circuit includes a first signal transmission line to transmit a first signal indicating the presence of two or more logical signals to be detected and a second signal transmission line to transmit a second signal indicating the presence of one or more of the logic signals to be detected. Each of the first and second signal transmission lines includes logic circuits. The signal detection circuit may have a hierarchical structure.

Signal detection circuit for detecting multiple match in arranged signal lines

A CAM (content addressable memory) device capable of flexibly coping with a wide range of user requirements with respect to operation speed and/or power consumption has operation mode setting means, generates a higher or lower internal voltage than an external power-supply voltage depending on the setting, and at least part of the internal circuit is operated by the internal voltage. In particular, the high level of the search-bit line and/or the high level of the match line are preferably set to the internal voltage. Also, the CAM device has bit line amplitude adjusting means for adjusting the amplitude of the bit line depending on the setting of the operation mode setting means and/or match line amplitude adjusting means for adjusting the amplitude of match line on which a search result is output, and thus is capable of appropriately changing the operation speed and power consumption depending on the setting.

Content addressable memory device having an operation mode setting means

In a content addressable memory (CAM), a spare CAM word serving as a redundant circuit is mounted in addition to a plurality of CAM words, and a storage section for holding information indicating whether there is a defective CAM word in the plurality of CAM words, and if there is one or more defective CAM word, address information of the defective CAM word. Control is applied according to the address information of the defective CAM word such that the defective CAM word is replaced with the spare CAM word. The search output of the defective CAM word is replaced with that of the spare CAM word. The spare CAM word serving as a redundant circuit is mounted without increasing a circuit scale and an output delay time, and a produce yield is improved.

Content addressable memory having redundant circuit

A content addressable memory device includes a storage bit line pair for reading storage data from and writing storage data to a content addressable memory cell, a search bit line pair, wired independently from the storage bit line pair, for providing search data to the content addressable memory cell, and a first unit for realizing a smaller swing in the level of the search bit line pair by setting the potential of the search bit line pair to an intermediate potential between a power source potential and a ground potential during match searching, and/or a second unit for realizing a smaller swing in the level of a match line by setting a precharge level of the match line to the intermediate potential between the power source potential and the ground potential.

Content addressable memory with potentials of search bit line and/or match line set as intermediate potential between power source potential and ground potential

A detection circuit detects the timings of transitions of two node signals. The detection circuit has two nodes A and B, a P-channel transistor and an N-channel transistor provided between a power supply and a ground so as to be connected in series in the order of the power supply, the P-channel transistor, and the N-channel transistor, and each of the gates thereof is connected to each of the two nodes A and B, and a floating-preventing latch circuit connected to a connection node formed by the P-channel transistor and the N-channel transistor. Particularly, in the detection circuit, the gate of the P-channel transistor is connected to the node A and the gate of the N-channel transistor is connected to the node B in which the two node signals A and B are initially LOW, the node signal A rises to HIGH first, then the node signal B rises to HIGH, the node signals A and B remain HIGH for a predetermined period, the node signal B falls to LOW first, and then the node signal A falls to LOW. Also, a detection circuit for detecting the timing of charge and discharge completion of the bit line for use in a semiconductor memory according to the present invention is provided.

Detection circuit for detecting timing of two node signals

An associative memory to which an encoder is applied has a plurality of associative memory subblocks each having a plurality of memory words. A hit flag resulting from match retrieval of retrieval data and the contents of the memory word, and an empty flag indicating whether or not the contents of the memory word are valid as objects for match retrieval are output from each memory word of each associative memory subblock. The address of an invalid memory word is readily controllable since the address of the memory word corresponding to the empty flag can be output as in a case where the address of the memory word corresponding to the hit flag is output. Moreover, since the hit flag and the empty flag are allowed to share a detection line with each other for common use in this encoder, the layout area of the associative memory is reduced and it is possible to build up a high-density associative memory.

Hierarchical encoder including timing and data detection devices for a content addressable memory

Hierarchical encoder including timing and data detection devices for a

A semiconductor integrated circuit includes a memory unit that receives data that is to be searched for and matches the data to be searched for with previously stored data; an encoder unit that receives and encodes the memory address of the matched data; and a decoder unit that receives and decodes the encoded memory address and accesses a predetermined word of the memory unit on the basis of the decoded memory address, and the encoder unit and the decoder unit are positioned adjacent to each other on a first side of the memory unit. Consequently, it is possible to connect with a shortened distance the memory address signal lines which are output from the encoder unit and input into the decoder unit to reduce the delay time caused by the wiring, thereby making it possible to improve the operational speed of the circuitry.

Integrated circuit for content addressable memory

A encoder has a prefetch circuit or a flag data sense circuit built into the priority encoder provided for a CAM block. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and this makes the encoder best suitable for a large capacity CAM which is required to operate at high speed. Moreover, a semiconductor integrated circuit of the present invention detects the differential current between the current flowing through one signal line and the reference current flowing through the other signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock, and it can operate as the timing control circuit to previously notify the encode termination of the hit signal in the subblock of the encoder described above. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed. Moreover, a dynamic sense amplifier is able to operate with a great operating margin.

A Content Addressable Memory (CAM) encoder comprises either a prefetch circuit or a flag data sense circuit. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and enables a large capacity CAM to operate at high speeds. Moreover, a semiconductor integrated circuit detects the differential current between the current flowing through a first signal line and the reference current flowing through a second signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock and operates as the timing control circuit to predict the termination of the encoding operation. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed.

Growing community of inventors

Mihama-ku, Japan

Naoki Kanazawa