Renesas Technology Corp.

Renesas Electronics Corporation

Naoki Izumi

Akira Yamazaki

Shunichi Abe

Tetsuya Uebayashi

Masahiro Matsumoto

Atsushi Ishii

Hiroyuki Chibahara

Koji Bando

Kazuyuki Misumi

Tatsuhiko Akiyama

A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.

Semiconductor device and method for manufacturing the same

To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.

Semiconductor device and method of manufacturing same

Size of a chipping is made small, suppressing blinding of a blade, when performing dicing of a wafer. When cutting a wafer, cutting is performed so that the portion of a V character-shaped shoulder may enter below the front surface of a wafer (depth Zfrom a substrate front surface) using the metal-bond blade which includes the abrasive particle whose fineness number is more than #3000, and whose point is V character form. By processing it in this way, cutting resistance goes up and blinding of a blade can be prevented. Hereby, the size of a chipping can be suppressed small, preventing blinding of a blade.

Manufacturing method of semiconductor device

A semiconductor chip, substrate employing plural bonding steps to ensure complete bonding particularly of peripheral edges. Embodiments include placing an adhesive layer on a chip mounting substrate positioned on a first supporting device, pressing a semiconductor chip against the chip mounting substrate to bond the semiconductor chip temporarily to the chip mounting substrate temporarily bonded chip on a second supporting device, and applying chip to straighten warpage and to bond the chip entirely to the chip mounting substrate.

Method of attaching a semiconductor chip to a chip mounting substrate

In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.

Semiconductor apparatus utilizing a preparatory stage for a chip assembly

A semiconductor device and a manufacturing method thereof are provided with downsizing and densification achieved by reducing the thickness of the semiconductor device without increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed to overlap in the range of height with the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, a wire connects the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wire. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.

Semiconductor device

A section of predetermined geometry and area is provided on or in a die pad of a lead frame and taken as a mark to be used for checking the position of a semiconductor chip. If the semiconductor chip is placed outside an allowable range in the X direction, the semiconductor chip overlaps the mark, thereby changing the geometry of an observable portion (slanted portion) of the mark. By means of the change, a positional deviation of the semiconductor chip in the X direction can be ascertained. A positional deviation of the semiconductor chip in Y direction is determined, by observing whether or not an electrode is situated between extensions of sides of a certain portion of the section.

Lead frame

Semiconductor device, method of fabricating the same and semiconductor device fabricating apparatus

A semiconductor device and a manufacturing method for downsizing and densification achieved by reducing the thickness of the semiconductor device without an increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed overlapping in height the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, wires connect the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wires. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.

Growing community of inventors

Tokyo, Japan

Naoki Izumi