Fujitsu Semiconductor Limited

Fujitsu Corporation

Naoki Idani

Ryota Nanjo

Toshiyuki Karasawa

Manabu Sakamoto

Takashi Watanabe

Tetsuya Shirasu

Satoshi Takesako

Tetsuya Shirazu

Toshiyuki Isome

A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Method for fabricating semiconductor device

An oxide film is formed on an inner surface of a via hole in which a through electrode is to be formed, and thereafter a Cu film is embedded in the via hole. When an excess Cu film formed on a first interlayer insulating film is removed by a CMP method, the oxide film is also polished and reduced in thickness. Using the oxide film reduced in thickness as a hard mask, a wiring trench is formed in the first interlayer insulating film. At this time, the oxide film is further reduced in thickness. After a conductive material is embedded in the wiring trench, an excess conductive material is removed by polishing. At this time, the remaining oxide film is removed entirely by the polishing.

Method for manufacturing semiconductor device

A semiconductor device manufacture method includes: forming an insulating film above a semiconductor substrate; etching the insulating film to form a dummy groove having a first depth, a wiring groove having a second depth deeper than the first depth, and a via hole to be disposed on a bottom of the wiring groove; depositing a conductive material in the dummy groove, wiring groove and via hole and above the insulating film; and polishing and removing the conductive material above the insulating film.

Semiconductor device manufacture method and semiconductor device

A front surface of the wafer is contacted with a straight-shaped front surface cleaning brush, and a pressure is applied on the front surface cleaning brush from both ends to enlarge the diameters in both end portions of the front surface cleaning brush. The front surface cleaning brush rotates with a shaft being an axis. An inner surface of the front surface cleaning brush is directly in contact with a surface of the shaft. The front surface cleaning brush is composed of a single structure made of synthetic resin.

Cleaning apparatus and cleaning method for wafer

A polishing method includes a first polishing step of halfway polishing a film to be polished formed on a substrate, and a second polishing step of further polishing the polished film, wherein a first film thickness profile showing an in-plane distribution of a film thickness of the polished film after the second polishing step for a first substrate is measured, and the first polishing step for a second substrate is executed to obtain a second film thickness profile which has a size relation in a film thickness opposite to the first film thickness profile.

Polishing method, polishing apparatus, and method for manufacturing semiconductor device

The method comprises the step polishing the surface of a film-to-be-polished formed over a semiconductor substratewith a polishing pad while a polishing slurry containing abrasive grains, and an additive of a surfactant is being supplied onto the polishing padto thereby planarize the surface of the film-to-be-polished, and the step of further polishing the surface of the film-to-be-polished with the polishing pad while the polishing slurry and water are being supplied onto the polishing pad, after the surface of the film-to-be-polished has been planarized. In the finishing polish, not only deionized water but also the polishing slurry are supplied on to the polishing pad, a position for the polishing slurry to be supplied to and a position for the deionized water to be supplied to are suitably set, and a ratio of a supply amount of the polishing slurry and a supply amount of the deionized water is suitably set, whereby the intra-plane film thickness of the film-to-be-polished as finish-polished can be uniform.

Semiconductor device fabrication method

A wafer on which a CMP processing is completed is rotated. A front surface cleaning brush and a rear surface cleaning brush are made contact both surfaces of the wafer while being rotated. After the front surface cleaning brush and the rear surface cleaning brush are made to contact the wafer, both end portions of the front surface cleaning brush and the rear surface cleaning brush are deformed by means of pressurizing both ends of the front surface cleaning brush and the rear surface cleaning brush by pressure portions. That is, the both end portions of the front surface cleaning brush and the rear surface cleaning brush are compressed to enlarge diameters in the both end portions. As a consequence, the entire front surface of the wafer is made to contact the front surface cleaning brush substantially evenly, even if the wafer is warped into a shape of a mound. Therefore, a cleaning efficiency of the outer peripheral portion of the wafer improves.

A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the polished surface to an alkaline second cleaning fluid after the first exposing.

Method of manufacturing a semiconductor device and a semiconductor manufacturing equipment

Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface into first sub-regions; optimizing a coverage ratio of hard-to-polish regions in the first sub-regions to fall in a first predetermined range corresponding to the first sub-regions; dividing the substrate surface into second sub-regions different from the first sub-regions; and optimizing a coverage ratio of the hard-to-polish regions in the second sub-regions to fall in a second predetermined range corresponding to the second sub-regions, wherein patterns having a shorter edge of 5 &#x3bc;m or less are excluded from the optimization.

Designing and fabrication of a semiconductor device

The electronic device includes a plurality of layout regions each including a plurality of patterns defined by a buried structure buried in a substrate. For each of the layout regions, in each of the layout regions, the minimum space between the patterns, and a maximum area percentage allowed for the patterns in the layout region are defined based on a size of the layout region. In larger one of the layout regions, the minimum space between the patterns in the region is set larger.

Electronic device and method for designing the same

Designing a semiconductor device layout using polishing regions

A designing method of an electronic device is provided. An STI structure, a wiring structure and the like defines a first area ratio range and a second area ratio range that are permissible in order to obtain satisfactory polishing results. A region to be polished is divided into first smaller areas, an area ratio of each of which is adjusted to meet the first area ratio range. The region to be polished is divided into second smaller areas, which are larger than the first smaller areas. An area ratio of each is adjusted to meet the second area ratio range, thereby providing satisfactory planarity of the region to be polished without producing depressions due to erosion caused by differing polishing speeds caused by differing densities of the regions to be polished.

Growing community of inventors

Kawasaki, Japan

Naoki Idani