Texas Instruments Corporation

Lsi Logic Corporation

Naoki Hayashi

Tuan Q Dao

Shannon A Wichman

Vijayanand Angarai

Rekha Suryanarayana

In hardware multipliers, the generation of partial products is a necessary step in the process known to the art for efficient production of a final product. A way to increase the speed of hardware multipliers is through the use of the Booth algorithm. The alternate Booth partial product generation for hardware multipliers of the present invention is directed to a method and apparatus for eliminating the encoding of the bits of the multiplier prior to entering the partial product generating cell of the present invention which may result in less hardware and increased speed.

Alternate booth partial product generation for a hardware multiplier

A microprocessor (5) having an on-chip floating-point unit, or FPU, (31) is disclosed. Snoop logic (37) is present in the integer pipeline to detect the presence of floating-point load instructions, in which floating-point operands are retrieved from system main memory or from on-chip cache memory (6, 16.sub.d, 18) by load/store units 40. For such operations in which the floating-point operands are of single precision or double precision, immediate formatter (70) receives the retrieved operands on load/store buses (LOAD.sub.-- DATA0, LOAD.sub.-- DATA1) and reformats the operands into a higher precision format for use internally by FPU (31). Rebias circuitry (78) is provided within immediate formatter (70) to change the bias of the exponent portion of the reformatted floating-point operands. Selection of the appropriate operand for application to the execution stages (56, 58, 60) of FPU (31) is made by a multiplexer (74) responsive to control signals (BSEL) derived from load/store directives detected by snoop logic (37). The operation of the immediate formatter (70) enables the reformatting of single precision and double precision floating-point operands within the same machine cycle as their receipt on load/store buses (LOAD.sub.-- DATA0, LOAD.sub.-- DATA1), thus improving performance of microprocessor (5).

Immediate floating-point operand reformatting in a microprocessor

A microprocessor (5) having an on-chip floating point unit (31) is disclosed. According to the disclosed embodiments, the floating-point unit (31) is arranged in pipelined fashion, and permits out-of-order execution of instructions in the event that an instruction generates an exception, such as an underflow condition. Writeback queue control circuitry (70) is provided, which includes a writeback queue buffer (74) and a multiplexer (72). The multiplexer (72) is under the control of writeback queue control logic (75), and selects either the state of the writeback bus (WB) or the contents of the writeback queue buffer (74) for application to router circuitry (54), and thus writeback to a register file (39). Upon detection of an exception, the state of the writeback bus (WB) is forwarded to the execution units (56, 58, 60) for exception handling according to microcode, with a portion of the floating-point pipeline being flushed. Other instructions may execute, however, with their results stored in writeback queue buffer (74) until completion of the reformatting of the result having the exception. The contents of the writeback queue buffer (74) may be forwarded to the router circuitry (54) for writeback, and the floating-point status word (FSW) updated, in program order. Any of the results stored in the writeback queue buffer (74) that cause an exception may similarly be handled by the microcode sequence.

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Dallas, TX, United States of America

Naoki Hayashi