Fujitsu Corporation

Naoki Hara

Naoya Okamoto

Hitoshi Tanaka

Shirou Ozaki

Yoshihiro Nakata

Tsuyoshi Takahashi

Masashi Shima

Toshihiro Ohki

Masahiko Takikawa

Shigeru Kuroda

Yusuke Kumazaki

Shuichi Tanaka

A high-frequency circuit board includes: a first insulating layer having a first dielectric constant; a first metal layer provided to stack over the first insulating layer; a second insulating layer provided to stack over the first metal layer, and having a second dielectric constant lower than the first dielectric constant; a second metal layer provided to stack over the second insulating layer, on which a compound semiconductor device is mounted; and first vias penetrating the second insulating layer and connecting the first metal layer with the second metal layer.

High-frequency circuit board and antenna module

A semiconductor device includes a semiconductor layer structure, and gate, drain and source electrodes provided on the semiconductor layer structure, the gate electrode being located between the drain and source electrodes. A depletion modulating part is located between the gate electrode and the drain electrode and includes portions spaced apart from each other in a gate-width direction.

Semiconductor integrated circuit device

A first surface layer made of compound semiconductor material is defined in a surface area of a substrate. A first intermediate layer is formed on the surface layer, the first intermediate layer being made of compound material having Ga as a III group element and S as a VI element and having a thickness of at least two monolayers or thicker. A first electrode is formed on the first intermediate layer, being electrically connected to the first surface layer with an ohmic contact.

Semiconductor device with ohmic contacts on compound semiconductor and manufacture thereof

An undoped GaAs layer and a GaAs active layer are formed on a GaAs semiconductor substrate in that order, and a surface of the GaAs active layer is inactivated. Thereafter, a wafer composed of the GaAs semiconductor substrate, the undoped G&As layer and the GaAs active layer is annealed at temperatures ranging from 570 to 580.degree. C. in a molecular beam epitaxy apparatus. Thereafter, the wafer is maintained at temperatures ranging from 350 to 500.degree. C., and an insulating layer made of amorphous GaAs is formed on the GaAs active layer while using tertiary-butyl-gallium-sulfide-cubane '((t-Bu)GaS).sub.4 ' as a source of the insulating layer. Thereafter, the insulating layer is patterned according to a photo-lithography method to form a gate insulating layer on the GaAs active layer. Thereafter, a source electrode and a drain electrode are formed on both sides of the gate insulating layer to arrange the source and drain electrodes separated from each other on the GaAs active layer, and a gate electrode is formed on the gate insulating layer.

Compound semiconductor apparatus and method for manufacturing the

An undoped GaAs layer and a GaAs active layer are formed on a GaAs semiconductor substrate in that order, and a surface of the GaAs active layer is inactivated. Thereafter, a wafer composed of the GaAs semiconductor substrate, the undoped GaAs layer and the GaAs active layer is annealed at temperatures ranging from 570 to 580.degree. C. in a molecular beam epitaxy apparatus. Thereafter, the wafer is maintained at temperatures ranging from 350 to 500.degree. C., and an insulating layer made of amorphous GaAs is formed on the GaAs active layer while using tertiary-butyl-gallium-sulfide-cubane '((t-Bu)GaS).sub.4 ' as a source of the insulating layer. Thereafter, the insulating layer is patterned according to a photo-lithography method to form a gate insulating layer on the GaAs active layer. Thereafter, a source electrode and a drain electrode are formed on both sides of the gate insulating layer to arrange the source and drain electrodes separated from each other on the GaAs active layer, and a gate electrode is formed on the gate insulating layer.

Compound semiconductor field effect transistor having an amorphous gas

A field-effect transistor including a channel layer, a source electrode, a drain electrode, a high-resistance layer provided on the channel layer between the source electrode and the drain electrode and a gate electrode provided in an opening formed in the high-resistance layer, wherein the high-resistance layer is defined by a first side-wall facing the source electrode and a second side-wall facing the drain electrode, such that the first side-wall is separated from the source electrode.

Field effect semiconductor device having a reduced leakage current

A field effect transistor includes a substrate of a compound semiconductor material, source and drain regions formed in the substrate, a channel region defined between the source and said drain regions, a gate electrode provided on the substrate so as to cover the channel region, and a pair of diffusion suppressing regions provided in the substrate respectively at both lateral ends of the channel region, each of the diffusion suppressing regions containing an electrically inert element that suppresses a diffusion of a dopant element therethrough.

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Kawasaki, Japan

Naoki Hara