Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Naoki Hamanaka

Teruo Tanaka

Tatsuo Higuchi

Junji Nakagoshi

Shigeo Nagashima

Shigeo Takeuchi

Yuji Tsushima

Naohiko Irie

Keitaro Uehara

Shinichi Kawamoto

Masabumi Shibata

Hideya Akashi

Toru Shonai

Yasuhiro Ogata

Koichiro Omoda

Taturu Toba

Tsuyoshi Tanaka

Takehisa Hayashi

Tetsuhiko Okada

Hiroyuki Chiba

Shinichi Shutoh

Yasuhiro Ishii

Yoshiko Yasuda

Tetsuya Mochida

Makoto Nohmi

Akira Muramatsu

Masamori Kashiyama

Kazuo Nakao

Kousuke Sakoda

Ikuo Yoshihara

Atsushi Nakajima

Youichi Tanaka

Shin'ichi Shutoh

Daisuke Yoshida

Shinji Fujiwara

Akira Yamagiwa

Toshiaki Tarui

Yasuhiro Inagami

Toshio Okochi

Kenichi Ishibashi

Yoshiko Tamaki

Yooichi Shintani

Hiroaki Fujii

Mitsuru Nagasaka

Kazuo Ojima

Hideki Murayama

Sigeo Ihara

Kyoko Iwasawa

Hideo Wada

Tatsuru Toba

Tsutomu Goto

Shisei Fujiwara

Hiromitsu Maeda

Yoshinori Wakai

Mitsuyoshi Igai

Koichiro Omada

Mikiko Suzuki

Disclosed are a virtual computer system and method, wherein computer resources are automatically and optimally allocated to logical partitions according to loads to be accomplished by operating systems in the logical partitions and setting information based on a knowledge of workloads that run on the operating systems. Load measuring modules are installed on the operating systems in order to measure the loads to be accomplished by the operating systems. A manager designates the knowledge concerning the workloads on the operating systems through a user interface. An adaptive control module determines the allocation rations of the computer resources relative to the logical partitions according to the loads and the settings, and issues an allocation varying instruction to a hypervisor so as to thus instruct variation of allocations.

Virtual computer systems and computer virtualization programs

Disclosed herein is a computer system provided with a mechanism for connecting a single port disk to an active server and the disk to a standby server when in a fail-over processing. An 'add_pci' command issued from a clustering program is used to let a control program change the allocation of a PCI slot while an interruption signal issued to a standby server permits an ACPI processing routine to hot-add a PCI card that includes the disk unit on the subject guest OS.

Fabric and method for sharing an I/O device among virtual machines formed in a computer system

A virtual computer system including a reallocation means, in which a plurality of LPAR are operated by logically dividing physical resources composing a physical computer exclusively or in time dividing manner so as to dynamically change reallocation of physical resources among each of LPARs. Based on load conditions measured by an application or an OS of each LPAR, physical resource allocation to each LPAR is determined, thereby conducting reallocation of LPAR.

Virtual computer system with dynamic resource reallocation

Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.

Shared memory multiprocessor system

Disclosed are a virtual computer system and method, wherein computer resources are automatically and optimally allocated to logical partitions according to loads to be accomplished by operating systems in the logical partitions and setting information based on a knowledge of workloads that run on the operating systems. Load measuring modules are installed on the operating systems in order to measure the loads to be accomplished by the operating systems. A manager designates the knowledge concerning the workloads on the operating systems through a user interface. An adaptive control module determines the alalocation ratios of the computer resources relative to the logical partitions according to the loads and the settings, and issues an allocation varying instruction to a hypervisor so as to thus instruct variation of allocations.

Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit inter-connecting the node but directly to the unit designated by the unit information.

Shared memory multiprocessor performing cache coherence control and node controller therefor

In a multiprocessor system of a main memory shared type having a plurality of nodes connected each other through signal lines; each of the plurality of nodes includes CPUs having caches therein, a main memory, and a node controller for performing communication control between the CPUs, main memory and ones of the nodes other than its own node. The node controller has a communication controller for controlling communication interface between the plurality of nodes, a crossbar for determining a processing sequence of memory access issued from at least one of the plurality of nodes to be directed to the main memories of the plurality of nodes, and crossbar controller for making valid or invalid the crossbar.

Node controller for performing cache coherence control and memory-shared multiprocessor system

A cache coherence control system for a multi CPU system having a plurality of CPU nodes, memory nodes and I/O nodes interconnected by a network. Each CPU node control circuit has an access right memory for managing an access right of the node in the unit of an extended node larger than a block size of the internal cache of a CPU. When a memory access is performed, the access right memory is referred to, and if the node has an access right to the extended block including a target block, the block is accessed without cache coherence control at other nodes.

CACHE COHERENT CONTROL SYSTEM FOR NETWORK NODES ALLOWS CPU OR I/O DEVICE TO ACCESS TARGET BLOCK WITHOUT CACHE COHERENCE CONTROL, IF ASSOCIATED NODE HAS ACCESS RIGHT IN AN ACCESS RIGHT MEMORY TO TARGET BLOCK

In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

Multi-processor system and its network

A cache memory unit that preferentially stores specific lines at the cache memory, according to the program nature, dynamically changes the priority ranks of lines, and increases the cache memory hit rate. For this purpose, the lines to be accessed by a processor are divided into groups and definitions of the groups are set in a group definition table; a policy by which to store lines belonging to the groups into the cache memory is set in a policy table; and storing lines into the cache memory is executed, according to the group definitions and the policy of storing set in the tables.

Cache control system

Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.

An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs. When the response order is changed, the response side interface unit issues a command, which changes the value of the request side queue pointer, to inform the request side interface unit of the change in the order.

Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer

A multiprocessor system can reduce a broadcast for cache memory consistency control with memory access from an I/O device. The multiprocessor system is provided with a cache memory identifier or an owner tag, and a block length table for recording a memory write block length of the I/O device. The cache memory identifier records that the cache has an exclusive copy. The owner tag records that there is no cache memory having an exclusive copy. If there is an exclusive copy during read through the I/O device, a read request is issued to both a cache holding the copy and a memory. If it is recorded that the copy is not present, data are directly read from the memory. Moreover, when a write block length is recorded in the block length table during write, whole blocks are collected to issue a request for invalidation from the cache and the request is directly written to the memory after the invalidation is completed.

Multiprocessor system

In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation. On the other hand, when there is no possibility that the memory to be accessed is cached, this memory access command is transferred only to the target node in yan one-to-one correspondence.

Multiprocessor system and methods for transmitting memory access transactions for the same

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Tokyo, Japan

Naoki Hamanaka