Hitachi, Ltd.

Naokatsu Suwanai

Hiroyuki Uchiyama

Yoshiyuki Kaneko

Kozo Watanabe

Hiroyuki Miyazawa

Kyoichiro Asayama

Atushi Ogishima

Masaki Nagao

Hiroki Soeda

Kazuya Endo

Takashi Yoneoka

Osamu Tsuchiya

Yasuhide Fujioka

In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

Semiconductor memory circuit device and method for fabricating a

A semiconductor integrated circuit device is provided in which an interlayer insulation film deposited on a semiconductor chip includes a boron-containing silicon oxide film and a second film deposited on the boron-containing silicon oxide film. A guard ring is disposed adjacent to the periphery of the semiconductor chip, and a slit is disposed between the guard ring and the periphery of the chip. The depth of the slit is selected such that cracks formed on the boundary between the BPSG film and the second film are inhibited by the slit from intruding further along the boundary to the inside of the chip, thereby preventing moisture or obstacles from reaching the inside of the chip through the cracks.

Semiconductor integrated circuit device including boron-doped phospho

Method of making a semiconductor memory circuit device

In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region, which is a memory cell array region, a first MISFET having a gate electrode and source and drain regions; first and second capacitor electrodes and a dielectric film extended over a first insulating film and over the gate electrode; a second insulating film disposed on the second capacitor electrode; a third insulating film interposed between the first insulating film and first capacitor electrode; and a first wiring positioned on the second insulating film. In a second region of the device, which is a peripheral circuit region, there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a second insulating film on a third insulating film, the third insulating film being interposed between the first and second insulating films; and a second wiring on the second insulating film. The second wiring is formed by the same level conductor layer as that forming the first wiring. Similarly, the first through third insulating films of the first region are correspondingly associated with the first through third insulating films of the second region, respectively.

Semiconductor memory circuit device and method for fabricating same

A semiconductor integrated circuit device having a wiring line of aluminum film or aluminum alloy film covered with a silicon insulation film and connected to the semiconductor region formed on the principal surface of a single crystal silicon substrate, with a polycrystalline silicon film interposed, wherein said silicon film is a polycrystalline silicon film composed of large crystal grains which is formed by depositing in amorphous state and then heat-treating the deposited film, said polycrystalline silicon film reduces the amount of silicon atoms which separates out in said wiring line. Also said wiring line is provided with a shielding film which is disposed between said insulation film and at least the upper surface and lower surface of said wiring line and which prevents silicon atoms from separating out from said insulation film. A process for manufacturing a semiconductor integrated circuit device which comprises the steps of depositing an amorphous silicon film on the principal surface of said semiconductor region, and performing heat treatment on said silicon film, thereby converting the amorphous silicon film into a polycrystalline silicon film composed of large crystal grains.

Method of making semiconductor integrated circuit device with

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Koganei, Japan

Naokatsu Suwanai