Kabushiki Kaisha Toshiba

Naoka Yano

Naoyuki Tamura

Yukinori Muroya

An improved arithmetic circuit for accumulative operation for use in digital signal processors, microprocessors and so forth is described, in which the pipelined control becomes effective during accumulative operation by eliminating idling stages in the pipeline structure. In accordance with the improved arithmetic circuit, during accumulative operation, the next operation is initiated with intermediate results of the current operation while the current operation is being executed and not yet completed so that it is possible to improve the speed of accumulative operation and reduce the scale of integration.

Arithmetic circuit for accumulative operation

In division process of restoring type or non-restoring type, a partial remainder is compared with a divisor in terms of absolute value. If the partial remainder is larger or both are equal, a quotient of its column is regarded as 1 and if small, the quotient of that column is regarded as 0 upon this division.

Division circuit not requiring taking complements of divisor, dividend and remainder

Upon execution of four sets of m/2 bit&times;n/2 bit multiplication, four multiplicand selectors select m/2-bit multiplicands respectively and four multiplicator selectors select corresponding n/2-bit multiplicators respectively, then the selected m/2-bit multiplicands and n/2-bit multiplicators are input into four multipliers, and then four sets of m/2 bit&times;n/2 bit multiplication are executed in parallel. Upon execution of m bit&times;n bit multiplication, the four multiplicand selectors select upper or lower m/2-bit multiplicands respectively and the four multiplicator selectors select upper or lower n/2-bit multiplicators respectively, then the selected m/2-bit multiplicands and n/2-bit multiplicators are input into the four multipliers respectively, then multiplication results of (lower m/2 bits of m bits)&times;(lower n/2 bits of n bits) and (upper m/2 bits of m bits)&times;(upper n/2 bits of n bits) out of four multiplication results of the four multipliers are connected by a connector, and then the connected multiplication results and the other two multiplication results are added by an adder with arranging in a predetermined bit location each other respectively.

High-efficiency multiplier and multiplying method

In division process of restoring type or non-restoring type, a partial remainder is compared with a divisor in terms of absolute value. If the partial remainder is larger or both are equal, a quotient of its column is regarded as 1 and if smaller, the quotient of that column is regarded as 0 upon this division.

Division circuit not requiring taking complements of divisor, dividend

A latch circuit receives complementary signals and consists of an nMOS transistor whose source is connected to an input terminal of the latch circuit and a series-connected circuit consisting of first and second pMOS transistors arranged between and connected to a drain terminal of the nMOS transistor and a high-potential power supply. The complementary signals are a first signal and a second signal that is an inversion of the first signal. Each of the signals has a pulse characteristic that rising time is longer than falling time. The latch circuit latches a quick fall by passing the first signal through the nMOS transistor. On the other hand, the latch circuit latches a slow rise by turning on the second pMOS transistor in response to a fall in the second signal.

Latch circuit and arithmetic unit having the same

In the first half of one cycle of a clock, a partial product generation circuit of each stage in a multiplication array generates partial products on the basis of one bit of the 16 low-order bits of multiplier data and the bits of multiplicand data. An accumulative addition circuit of each stage in the multiplication array accumulatively adds an initial value or an output from a previous accumulative addition circuit to the partial products to perform half necessary multiplication, writes the accumulative result in a latch as intermediate result data, and writes the predetermined number of bits of an output from the accumulative addition circuit of each stage at a predetermined bit position of the latch. In the second half of the clock, the partial product generation circuit of each stage generates partial products on the basis of one bit of an output from a latch holding the 16 high-order bits of a multiplier and the bits of the multiplicand data. In addition, the accumulative addition circuit of each stage accumulatively adds the intermediate result data or an output from a previous accumulative addition circuit to the partial products to perform the remaining half the calculation, and writes the final accumulative addition result and the predetermined number of bits of the output from the accumulative addition circuit of each stage in a latch.

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Tokyo, Japan

Naoka Yano