Matsushita Electric Industrial Co., Ltd.

Nippon Hoso' Kyokai

Matsushita Electrical Industrial Co., Ltd.

Nippon Hoso Kyokai, Both of

Naoji Okumura

Yosuke Izawa

Yutaka Nio

Masahiro Tani

Katsumi Terai

Hirohiko Sakashita

Yuichi Ninomiya

Kazuto Tanaka

Yoshimichi Ohtsuka

Hideyo Uwabata

Toshihiro Miyoshi

Tadashi Kawashima

Takushi Iwamoto

Satoshi Okamoto

Masaaki Fujita

Minoru Miyata

Kazuhito Tanaka

Toshichika Sato

Hisashi Arita

Atsuhisa Kageyama

Yutaka Nishikawa

Tomoko Morita

Kazunori Yamate

Hiroki Monta

Kazumi Kawashima

Masanobu Tanaka

Yasuaki Sakanishi

Toshiro Ohmura

Tetsuo Kutsuki

Toshiaki Kitahara

Kenji Ishikawa

Masanori Nakatsuji

Kazuyasu Yamamoto

Tsutomu Nishida

Yasuaki Uehara

Kouichirou Fue

Toshiohika Sato

Naoki Shintani

A write PLL circuit generates a write clock signal for writing a video signal into a line memory. A readout PLL circuit generates a read clock signal for reading out the video signal stored in the line memory. An inner pincushion distortion correction voltage generation circuit modulates a correction waveform in the horizontal scanning period of time by a correction waveform in the vertical scanning period of time, to generate an inner pincushion distortion correction waveform, and adds a DC correction pulse to the inner pincushion distortion correction waveform and outputs the inner pincushion distortion correction waveform as an inner pincushion distortion correction voltage. A capacitive coupling circuit superimposes the inner pincushion distortion correction voltage on an output voltage of a loop filter of the readout PLL circuit, and feeds the inner pincushion distortion correction voltage to a VCO as a control voltage.

Image distortion correcting device and image distortion correcting method

A parallel scanning circuit outputs a parallel scanning signal for making forward and backward scanning lines parallel. A vertical correlation detection circuit detects a portion where the change in luminance in the vertical direction exceeds a predetermined value on the basis of a luminance signal, and outputs a movement control signal representing the distance of movement on the screen of the scanning line. A retrace period reversion circuit reverses the lime axis of the movement control signal in a retrace period. A clamping circuit clamps the movement control signal to a predetermined DC voltage at the timing of horizontal synchronizing signal. A synthesizing circuit synthesizes the parallel scanning signal and the movement control signal, and feeds a synthesized signal as a vertical velocity modulation signal to a vertical velocity modulation coil.

Video display apparatus with vertical scan velocity modulation and video display method thereof

A ringing detector detects mosquito noise and ringing for outputting an image signal smoothed by a horizontal/vertical high-pass filter when mosquito noise and ringing are detected while outputting the image signal as such when neither mosquito noise nor ringing is detected, thereby properly correcting the image signal without reducing the texture specific to the image signal also in a portion continuously exhibiting fine details.

Noise detector, noise detection method, signal processor and signal processing method

A vertical HPF and a horizontal HPF receive a video signal , and extract only a high frequency component in the vertical/horizontal directions, respectively. Absolute value taking parts take an absolute value of the high frequency components, respectively, and change their values to positive values. A horizontal accumulating/adding part and a vertical accumulating/adding part accumulate/add an input signal so as to output a vertical one-dimensional signal and a horizontal one-dimensional signal, respectively, each periodically having a peak value in the respective vertical and horizontal directions. A horizontal peak detecting part detects a horizontal peak position according to the horizontal one-dimensional signal. A vertical peak detecting part detects a vertical peak position according to the vertical one-dimensional signal and identifies a format thereof. A binarization part obtains a block boundary image, according to the horizontal peak position and the vertical peak position, in which pixel positions having a peak are provided with 1 and remaining pixel positions are provided with 0. In this manner, even if a block boundary to eliminate block noise thereon is not clearly identified, it becomes possible to correctly detect and eliminate the block boundary.

Block noise detector and block noise eliminator

A video signal processing circuit synthesizes a video signal and a graphic signal on the basis of a display switching control signal, inverts a synthesized signal on the time axis for each of a forward scanning period and a backward scanning period, and output a display signal. A speed modulating signal control circuit inverts the binarized display switching control signal on the time axis for each of the forward scanning period and the backward scanning period, expands the pulse width thereof, and feeds the display switching control signal to a speed modulating signal generating circuit. The speed modulating signal generating circuit subjects a display signal to first-order differentiation, inverts the polarity of a differentiated signal in the backward scanning signal, sets a portion, corresponding to the graphic signal, in the differentiated signal on the basis of the display switching control signal at a zero level, and generates a speed modulating signal.

Image display and horizontal speed modulator

A video signal of an interlaced scanning system having 525 scanning lines and a vertical scanning frequency of 60 Hz is converted to a video signal having 1050 scanning lines and a vertical scanning frequency of 120 Hz, for displaying an image by bidirectional scanning. A vertical synchronizing signal is subjected to offset processing by a &frac14; horizontal scanning period when an odd field is started, thereby keeping interlaced relation between odd and even fields. The vertical synchronizing signal is subjected to offset processing by a &frac12; horizontal scanning period every frame, so that the scanning direction for each scanning line is reversed every frame.

Video display apparatus with scan conversion and reversion and a video display method using scan conversion and reversion

Apparatus for correcting vertical contours

A subpicture image signal vertical compression circuit for vertically compressing subpictures operating at respective synchronous timings different from that of the main picture when a plurality of image signals having respectively different synchronizations are displayed on an image display device. Depending on whether the field polarities of main and sub pictures are the same or not, the subpicture image signal vertical compression circuit generates suitable offsets for the first and the second fields to adjust the phases and prevent the inversion of the scan order in the vertical direction, at the first field and the second field of subpicture signal, after the phase adjustment to obtain a subpicture image with natural motion in the vertical direction.

Subpicture image signal vertical compression circuit

An automatic aspect ratio discrimination apparatus for detecting a picture starting position, a picture ending position and a subtitle ending position by generating three histograms segmented by two slice levels S and T at every line from a luminance signal Y at a comparison circuit and counters, judging when the line is black, a picture or a subtitle by inputting the obtained histograms to the comparison circuit, detecting lines varying from black to picture, from picture to black, and from subtitle to black at an edge detection circuit and judging if the lines varying from black to picture and from picture to black are stable in time or not at a temporal filter.

Apparatus for distinguishing between a plurality of video signal types,

A video signal compression apparatus extracts a specific value written in a read only memory at every system clock pulse. The specific value can be varied at every clock pulse. Therefore, for example, only the center cart of a picture can be horizontally compressed A FIFO memory may be used. It is possible to select a mode with a fixed compression ratio or a mode in which a compression ratio varies at every clock pulse. Further, the fixed compression ratio can be set from the outside. Display position or the picture can also be changed.

Video signal compression apparatus for horizontal compression of a video

A video signal compression apparatus extracts a specific value written in a read only memory at every system clock pulse. The specific value can be varied at every clock pulse. Therefore, for example, only the center part of a picture can be horizontally compressed. A FIFO memory may be used. It is possible to select a mode with a fixed compression ratio or a mode in which a compression ratio varies at every clock pulse. Further, the fixed compression ratio can be set from the outside. Display position of the picture can also be changed.

A high precision aspect ratio auto-discrimination apparatus used for display apparatuses and television receivers comprising: an apparatus for detecting the upper edge and lower edge of a letter box picture through detecting the average luminance of every horizontal scan period; an apparatus for detecting respective average luminance levels in a plurality of specific regions in one field picture controlled by a horizontal synchronous signal and a vertical synchronous signal; and, an aspect ratio discrimination section to which the outputs of said both apparatuses are input.

Average luminance level detection apparatus and aspect ratio

A phase locked loop circuit comprises a divider which is changed in a dividing ratio in compliance with a control signal applied thereto, the output of the divider is phase-compared with an input signal of the phase locked loop circuit. A phase-compared output is applied to a low pass filter to obtain a direct current component, and an oscillator is controlled by the direct current component.

Phase locked loop circuit

The invention relates to a video signal memory equipment comprising a FIFO memory for storing video data of video signals, and a control unit for controlling writing and reading in the FIFO memory, wherein the control unit receives a horizontal synchronizing signal of video signal in video data writing action, writes a specified number of video data from the beginning of video data of brightness signals of the horizontal scanning period sequentially into the FIFO memory, and reads out the specified number of video data upon every input of horizontal synchronizing signal, in video data reading action, in the written sequence as video data of that horizontal scanning period, thereby storing and producing the video data of video signals, whereby video data of each horizontal scanning period of video signals are continuously written into the FIFO memory by every specified number of pieces from the beginning, and are read out by every specified number of pieces upon every input of horizontal synchronizing signal, and hence the video data of video signals can be read out by dividing in every horizontal scanning period, and therefore the address generating device for dividing the data in every horizontal scanning period is not needed in this video signal memory equipment.

Memory equipment for writing/reading a defective video signal in a FIFO

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Mino, Japan

Naoji Okumura