Renesas Electronics Corporation

Naohito Suzumura

Kazuyuki Omori

Hideki Aono

Yoshihiro Oka

Kenichi Mori

Takeshi Furusawa

Kenichiro Sonoda

Hideaki Tsuchiya

Tetsuya Yoshida

Masakazu Okada

Takao Kamoshima

Makoto Ogasawara

Shoichi Fukui

Takahisa Furuhashi

Masatsugu Amishiro

An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.

Semiconductor device

In the semiconductor device, a first defect formation preventing film is formed on the first wiring side, and a second defect formation preventing film is formed on the second wiring side. when a ratio of an infrared absorption intensity corresponding to a bond between silicon and hydrogen to an infrared absorption intensity corresponding to a bond between silicon and oxygen is defined as an abundance ratio, the abundance ratio in the first defect formation preventing film is smaller than the abundance ratio in the second interlayer insulating film. The abundance ratio in the second defect formation preventing film is smaller than the abundance ratio in the second interlayer insulating film.

Semiconductor device and method of manufacturing the same

To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

Semiconductor device and method for manufacturing the same

A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.

A semiconductor device is provided in which reliability of the semiconductor device is improved by improving an EM characteristic, a TDDB characteristic, and a withstand voltage characteristic of the semiconductor device. An average diameter of first vacancies in a lower insulating layer which configures an interlayer insulating film of a porous low-k film for embedding a wiring therein, is made smaller than an average diameter of second vacancies in an upper insulating layer, and thereby an elastic modulus is increased in the lower insulating layer. Further, a side wall insulating layer which is a dense layer including the first vacancies having an average diameter smaller than the second vacancies is formed on the surface of the interlayer insulating film exposed on a side wall of a wiring trench.

A barrier insulating film is constituted from a first SiCN film formed with a tetramethylsilane gas flow rate lower than usual, a second SiCN film formed over the first SiCN film and formed with a usual tetramethylsilane gas flow rate, and a SiCO film formed over the second SiCN film.

In MRAM, a write wiring clad in a ferromagnetic film has been used to reduce a write current or avoid disturbances. Besides, a CuAl wiring obtained by adding a trace of Al to a Cu wiring has been used widely to secure reliability of a high reliability product. There is a high possibility of MRAM being mounted in high reliability products so that reliability is important. Clad wiring however increases the resistance of the CuAl wiring, which is originally high, so that using both may fail to satisfy the specification of the wiring resistance. In the semiconductor device of the invention having plural copper-embedded wiring layers, copper wiring films of plural copper-embedded clad wirings configuring a memory cell matrix region of MRAM are made of relatively pure copper, while a CuAl wiring film is used as copper wiring films of copper-embedded non-clad wirings below these wiring layers.

Semiconductor device and manufacturing method thereof

The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating filmsare formed. In the insulating filmsa contact hole is formed and a plug is embedded therein. Over the insulating filmin which the plug is embedded, insulating filmsare formed and an opening is formed in the insulating filmsand a wire is embedded therein. The insulating filmis an etching stopper film when etching the insulating filmin order to form the opening, containing silicon and carbon. The insulating filmhas a high hygroscopicity and the insulating filmhas a low moisture resistance, however, by interposing the insulating filmtherebetween and making the insulating filmhave a higher density of the number of Si (silicon) atoms than that of the insulating film, an electrically weak interface is prevented from being formed.

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Tokyo, Japan

Naohito Suzumura