Nippondenso Co., Ltd.

Denso Corporation

Toyota Jidosha Kabushiki Kaisha

Naohito Kato

Naoto Okabe

Norihito Tokura

Tsuyoshi Yamamoto

Yoshiyuki Miyase

Takeshi Matsui

Koichi Kato

Masahiro Yamamoto

Masami Yamaoka

Tomoatsu Makino

Masami Kojima

Yutaka Tomatsu

Yoshihiko Ozeki

Haruo Kawakita

Tohru Nomura

Kazuya Asaoka

Takahito Nishii

Sho Masuda

Yuji Kajita

Motoo Yamaguchi

Kasuhiro Yamada

Yoshiki Ishida

Etsuji Toyoda

A headlight control device provided in a vehicle to perform headlight control and to control a distribution of light irradiated from a light source is provided. The headlight control device includes: a determination unit that determines a presence and an absence of an obstacle in front of the vehicle and determines a position of the obstacle; a setting unit that sets up an area covering the obstacle as an intensified illumination area when the determination unit determines the presence of the obstacle, wherein the intensified illumination area is an area to which the light from the light source is irradiated in a manner different than a peripheral area of the intensified illumination area; and a controller that controls the distribution of the light irradiated from the light source so that the intensified illumination area set up by the setting unit has an illuminated zone and a non-illuminated zone.

Headlight control device and headlight

A single semiconductor power module includes a power semiconductor chip including an embedded IGBT (the power semiconductor switching-device) and a control semiconductor chip. The power semiconductor chip also includes a gate series resistor integrated therein as a resistor through which the control semiconductor chip drives the power semiconductor chip. In such a configuration, a gate wire between the gate series resistor and a gate has a small lead inductance and a small parasitic capacitance with respect to the ground.

Power semiconductor switching-device and semiconductor power module using the device

A head lamp device for a vehicle includes a DC power source, a diode array having a plurality of series-connected light emitting diodes and a current control circuit that supplies driving current to the diode array. The current control circuit is constituted of a current supply circuit, a voltage measuring circuit, a comparing circuit that compares the voltage drop with a reference value, a judging circuit for judging that there is a short-circuiting at any of the light emitting diodes based on the comparison by the comparing circuit, and a display unit for displaying an alarm when the judging circuit judges that there is a short-circuiting.

Vehicle head lamp device

An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a withstanding voltage between a semiconductor substrate and the buffer layer is lower than the withstand voltage of the pn junction at the edge of the diced cross-section. Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has wide area, breaks down, as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.

Insulated gate bipolar transistor and method of fabricating the same

A wide high concentration P,type region is formed on the surface of an N,type epitaxial layer formed on a P type substrate in the vicinity of the edge portion of a cell region in which a transistor device is formed. As a result, holes generated at the outside of the cell region mostly flow through the P,type region and reach to an emitter electrode. Therefore, the flow amount of the holes does not concentrate on a channel P well for forming a channel region of the transistor device at the cell edge portion, whereby a ruggedness against a latch-up phenomenon can be improved.

Insulated gate field effect transistor and manufacturing method of the same

An insulated gate type bipolar-transistor (IGBT) incorporates an excess voltage protecting function and drain voltage fixing function in a monolithic structure. Impurity concentration ND and the thickness of an n.sup.- type drain layer (3) is set so that a depletion region propagating from a p type base layer (7) reaches a p.sup.+ type drain layer at a voltage (V.sub.DSP) lower than a voltage (V.sub.DSS) at which avalanche breakdown is caused within the IGBT element when voltage is applied between the source and the drain.

Insulated gate type bipolar-transistor

An insulated gate field effect transistor comprising a semiconductor substrate having one side on which a cell area is composed of a plurality of first wells of a first conductivity type, each of the first wells containing a source region of a second conductivity type. A channel region is defined in the surface portion of the semiconductor substrate adjoining to the source region, and a gate electrode is formed, via a gate insulating film, at least over the channel region. A source electrode is in common contact with the respective source regions of the plurality of first wells. The semiconductor substrate has a drain electrode provided on another side. A current flows between the source electrode and the drain electrode through the channel being controlled by a voltage applied to the gate electrode. A guard ring area is disposed on the one side of the semiconductor substrate so as to surround the cell area. The source electrode has an extension connected to a second well of a second conductivity type formed in the one side between the cell area and the guard ring area to provide a by-pass such that, when a current concentration occurs within the guard ring area, the concentrated current is conducted directly to the source electrode in the cell area through the by-pass, thereby preventing the concentrated current from causing a forward biassing between the first wells and the source region.

Insulated gate field effect transistor having guard ring regions

The insulated gate bipolar transistor (IGBT) integrates the anti-excess voltage protection function and a drain voltage fixing function. When a voltage is applied across the drain electrode and the source electrode of the IGBT, a depletion zone propagates from a p-n junction between a p base layer and a n.sup.- drain layer toward inside of the n.sup.- drain layer. A critical electric field is also established, causing generation of a great number of electron-hole pairs due to impact ionization of carriers in or near the n.sup.- drain layer. Conduction exist between the drain electrode and the source electrode, at an applied voltage lower than a drain-source voltage at which the depletion region reaches a p.sup.+ drain layer through the n.sup.- drain layer, the applied voltage being equal to or lower than a critical voltage that causes generation of a great number of electron-hole pairs due to impact ionization of carriers in or near the n.sup.- drain layer below a p-n junction between a p-type guard ring and the n.sup.- drain layer.

Insulated gate bipolar transistor

This invention aims at suppressing a parasitic transistor operation of a vertical MOS device at the time of application of a noise current and improving the limitations of withstanding against destruction of the device. P base layers 3 constituting each unit cell of an n-channel DMOS device are partially connected by p extraction regions between the unit cells so as to short-circuit the p base layers to source electrodes 9 in regions Z2 through the extraction regions. Accordingly, an applied noise branches to a conventional path extending from a region Z1 to the source electrodes 9 through an n source layer 5 and a path extending from +regions Z2 to the source electrodes 9 through the p extraction regions 4. Since the p regions form one continuous region throughout the device as a whole, a local potential rise of the p base layer can be limited. Accordingly, the parasitic transistor operation can be suppressed and a breakdown voltage of the device can be improved.

Vertical semiconductor device with breakdown voltage improvement region

An ignition system for an internal combustion engine is provided which includes an ignition coil formed with a primary winding and a secondary winding and a switching element for interrupting a current flow through the primary winding of the ignition coil at given timing. The ignition coil has a secondary winding to primary winding turns ratio a which meets the condition of V.sub.D .multidot.a &gt;V.sub.r where V.sub.r is a required voltage of a spark plug of the engine and V.sub.D is a breakdown voltage of the switching element which is greater than or equal to 450 V.

Internal combustion engine ignition system

An insulated gate bipolar transistor has a reverse conducting function built therein. A semiconductor layer of a first conduction type is formed on the side of a drain, a semiconductor layer of a second conduction type for causing conductivity modulation upon carrier injection is formed on the semiconductor layer of the first conduction type, a semiconductor layer of the second conduction type for taking out a reverse conducting current opposite in direction to a drain current is formed in the semiconductor layer of the second conduction type which is electrically connected to a drain electrode, and a semiconductor layer of the second conduction type is formed at or in the vicinity of a pn junction, through which carriers are given and received to cause conductivity modulation, with a high impurity concentration resulting in a path for the reverse conducting current into a pattern not impeding the passage of the carriers. Therefore, the built-in reverse conducting function has a low operating resistance, a large reverse current can be passed, there is no increase in on-resistance, and the turn-off time can be shortened.

Insulated gate bipolar transistor with reverse conducting current

An IGBT chip includes a unit cell region and a guard ring region which surrounds the unit cell region. In the unit cell region, a plurality of IGBT unit cells are formed, each of which comprises a base layer, a source layer, a common gate electrode, a common source electrode, and a common drain electrode. In the guard ring region, at least one diffused layer making up a guard ring is formed. Further, an annular diffused layer is formed and is connected to the drain electrode. The annular diffused layer is disposed away from the outermost guard ring by a specified length. This length is such that the punch-through occurs before the avalanche breakdown voltage of the junction associated with the outermost guard ring. Therefore, the withstand voltage against the avalanche breakdown when surge voltage is applied to the drain electrode is improved.

A semiconductor device has a protective Zener diode formed through an insulation film to a silicon substrate having a power MOSFET formed thereon. The breakdown strength of the insulation film is substantially improved and the withstand voltage of the Zener diode can be set to a high value. A gate plate 11 electrically connected to an outer circumferential part of a p-type diffusion region 104 is installed, and element parts 112a-112c and equipotential plates 113a-133c constituting a Zener diode group 115 are formed. The equipotential plates 113a-133c hold a prescribed potential by Zener diode pairs 114 of the element parts 112a-112c.

Power semiconductor device with protective element

A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of the latch up and increase in the turn-off time due to the minority carriers concentrating into the border portion cell located adjacent to the pad region can be prevented.

Insulated gate bipolar transistor provided with a minority carrier

A p type pad well layer is formed at the surface of an n.sup.- type drain layer under a gate bonding pad and the surface thereof is provided with a p.sup.++ type pad layer to be provided with lower resistivity. The p.sup.++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, the introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p.sup.++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p.sup.++ type pad layer can be easily formed. The p.sup.++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of the latch up and increase in the turn-off time due to the minority carriers concentrating into the border portion cell located adjacent to the pad region can be prevented.

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Kariya, Japan

Naohito Kato