Nuvoton Technology Corporation Japan

Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Nuvuton Technology Singapore Pte. Ltd.

Nuvoton Technology Singapore Pte. Ltd.

Naohisa Hatani

Mitsuhiko Otani

Jiro Miyake

Norihide Kinugasa

Gorou Mori

Kouji Yamaguchi

Fumihito Inukai

Shinichi Ogita

Takayasu Kito

Yosuke Goto

Makoto Kawajiri

Takayasu Kitou

A voltage measurement device includes: a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a device address generating circuit which generates a device address according to a first address assignment command received from a preceding voltage detection circuit located at a preceding stage; and an address assignment command generating circuit which generates a second address assignment command according to the first address assignment command, and sends the second address assignment command to a next voltage detection circuit located at a next stage.

Voltage measurement device, voltage detection circuit, and device address generation method

A voltage measurement device is a voltage measurement device including a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a communication end information holding circuit which holds communication end information specifying, as at least one communication end position, at least one of the plurality of voltage detection circuits; and a communication control circuit which controls transfer for sending a communication command received from a preceding voltage detection circuit located at a preceding stage to a next voltage detection circuit located at a next stage, according to the communication end information.

Voltage measurement device, voltage detection circuit, and voltage detection method

A voltage detection circuit is provided for measuring each cell voltage of an assembled battery configured by connecting a plurality of cells in series. The voltage detection circuit is defined as a first voltage detection circuit. The voltage detection circuit includes a downstream communication circuit that communicates with a host apparatus to communicate with a plurality of voltage detection circuits connected in series with each other; a reply signal generation circuit that generates a reply signal containing data detected by the first voltage detection circuit; an upstream transfer circuit that transfers a signal received by the upstream communication circuit to downstream; a dummy current consumption circuit that consumes a predetermined dummy current; and a control circuit that controls the reply signal generation circuit, the upstream transfer circuit, and the dummy current consumption circuit to selectively operate any one of them.

Voltage detection circuit for voltage measurement apparatus for use in assembled battery system

A voltage detection circuit measures a plurality of cell voltages of an assembled battery configured by connecting a plurality of cells in series. The voltage detection circuit includes a plurality of input terminals connected to respective electrodes of the plurality of cells through a plurality of voltage detection lines; a multiplexer that periodically selects and outputs voltages of a plurality of cells in a group, a plurality of series cells configured as the group; an analog-to-digital (AD) converter that AD-converts an output voltage from the multiplexer and outputs digital data of the output voltage; and a control circuit that controls a timing for the selection by the multiplexer and a timing for the AD conversion. The control circuit switches over a time interval for which the multiplexer selects each of the cells to change a period of the AD conversion.

Voltage detection circuit measurement apparatus for use in assembled battery system

Each of n signal transition detection sections detects a transition of the signal level of at least one of a first input signal or a second input signal corresponding to the signal transition detection section. A time-division control section outputs a control pulse according to a system clock when a signal transition is detected by at least one of the n signal transition detection sections. Each of n output switching sections outputs either the first or the second input signal corresponding to the output switching section as a multiplexed signal according to the control pulse.

Time-division multiplexer and signal transmission apparatus

A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.

DLL circuit, imaging device, and memory device

A front-end signal processing circuit that stabilizes a black level of an output signal of an image sensor in a prescribed set level, without being influenced by a DC offset component of circuit elements making up a feedback loop, and an imaging device including such the front-end signal processing circuit, are provided. The front-end signal processing circuit includes a feedback loop made up of a luminance detecting/digitizing section and a black level clamp section, and clamps a black level of an output signal of an image sensor to a prescribed set level. The front-end signal processing circuit further includes an offset correction section. The offset correction section stores an offset value being a difference between a signal level of an OB region of the image sensor and the prescribed level, subtracts the offset value from a digital luminance signal corresponding to an effective pixel region of the image sensor, and outputs the obtained signal.

Front-end signal processing circuit and imaging device

A pipeline A/D converter of the present invention includes a plurality of stages each operating for A/D conversion and a digital computing portion that outputs an A/D converted signal based on a digital signal output from each of the stages. In each of the stages, an analog signal from the preceding stage is sampled by passive elements Cand Cin a first period, and one of the passive elements is used as a feedback element in a second period to perform adding/subtracting with respect to the signal sampled by the other passive element. By the control from the digital computing portion, a test signal Tink is used instead of an analog output signal Vo(k&#x2212;1), and a unique conversion-error value is detected and corrected based on the digital signal obtained by the operation of each of the stages. It is possible to obtain a high-resolution A/D convert that can suppress a conversion error caused by the relative error of capacitors used for analog signal processing without decreasing the speed of A/D conversion.

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Kyoto, Japan

Naohisa Hatani