Renesas Electronics Corporation

Sony Computer Entertainment Inc.

Sony Corporation

Sony Interactive Entertainment Inc.

Naohiro Nishikawa

Yuki Inoue

Yuichi Takagi

Tetsuji Tsuda

Masaru Hase

Masami Tako

Seiji Mochizuki

Katsushige Matsubara

Ren Imaoka

Seiji Murata

In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Semiconductor device and control method of semiconductor device

A data processing device, includes a bus, a demultiplexer which receives content including video data and audio data. A memory interface which is coupled to the bus, and which is connectable to a memory for temporarily accumulating the video data and the audio data output from the demultiplexer.

Content output device and program

A semiconductor device includes a central processing unit and a processor on one semiconductor substrate. The processor includes a buffer for storing a first register setting list and notifies the central processing unit of an access complete signal indicating completion of reading a second register setting list within a memory. The central processing unit changes the second register setting list within the memory based on the access complete signal and notifies the processor of an update request signal. The processor reads the second register setting list changed by the central processing unit into the buffer to update the first register setting list based on the update request information.

Semiconductor device

A semiconductor device includes a central processing unit and a processor on one semiconductor substrate. The processor includes a buffer for storing a register setting list and notifies the central processing unit of an access complete signal indicating completion of reading the register setting list. The central processing unit changes the register setting list within a memory based on the access complete signal and notifies the processor of an update request signal. The processor reads the register setting list changed by the central processing unit into the buffer based on the update request information.

A data processing device, includes a bus, a demultiplexer which receives content including video data and audio data. A memory interface is coupled to the bus, and is connectable to a memory for temporarily accumulating the video data and the audio data output from the demultiplexer.

A data processing device, includes a bus, a demultiplexer which is coupled to the bus, and which receives a content including video data and audio data. A memory interface which is coupled to the bus, and which is connectable to a memory for temporarily accumulating the video data and the audio data output from the demultiplexer in accordance with a delay amount.

At the time of device starting or channel switching in a content output device, even when buffering of a sufficiently large size is performed in order to address multimedia processing at the time of start of a device and content switching, slow reproduction in which video and audio are synchronized with each other can be performed without keeping a user waiting for a long time, and at an arbitrary reproduction rate with the extent of not giving the user feeling of unnaturalness. The broadcasting reception unit initializes the delay amount to a predetermined start value, then gradually increases it with lapse of time, and stops the increase when the delay amount reaches a predetermined end value. Video and audio are synchronously and slowly reproduced at a reproduction rate decided by an increment per unit time of the delay amount.

A system-level management unit generates a system processing and makes a processing request to a task allocation unit of a user-level management unit. The task allocation unit schedules the system processing according to a procedure of an introduced user-level scheduling. A processing unit assigned to execute the system processing sends a notification of acceptability of the system processing to a main processing unit, by halts an application task in appropriate timing or when the processing of the current task is completed. When the notification is received within the time limit for execution, the system-level management unit has the processing unit start the system processing.

Information processing device and information processing method

A thread status managing unit organizes a plurality of threads into groups and manages the status of the thread groups. A ready queue queues thread groups in a ready state or a running state in the order of priority and, within the same priority level, in the FIFO order. An assignment list generating unit sequentially retrieves the thread groups from the ready queue. The assignment list appends a retrieved thread group to a thread assignment list only when all threads belonging to the retrieved thread group are assignable to the respective processors at the same time. A thread assigning unit assigns all threads belonging to the thread groups stored in the thread assignment list to the respective processors.

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Tokyo, Japan

Naohiro Nishikawa