Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Shaibaura Denki Kabushiki Kaisha

Naohiro Matsukawa

Hiroshi Nozawa

Riichiro Shirota

Hiroshi Sukegawa

Junichi Miyamoto

Ryouhei Kirisawa

Takayasu Sakurai

Toshiharu Watanabe

Michiharu Matsui

Toshihiko Himeno

Mitsuo Isobe

Yoshihisa Mizutani

Keniti Imamiya

Shigeru Morita

Makoto Ichida

Sigeru Morita

Junichi Matsunaga

According to one embodiment, a memory system includes a nonvolatile semiconductor storage able to hold data, a temperature measurement section configured to measure the temperature of the semiconductor storage, a temperature varying section configured to change the temperature of the semiconductor storage, and a control circuit including a transmitter configured such that data received from a host is transferred to the semiconductor storage, and a temperature storage configured to store temperature information received from the temperature measurement section.

Memory system

A method of evaluating a semiconductor storage device of a floating gate type has calculating an electron density distribution of a tunnel insulating film of a memory cell by multiplying a change rate of a threshold voltage Vt of the memory cell of the semiconductor storage device with respect to the change of the logarithm of a time with &#x3b5;*Cr*2k/Tox/q (where &#x3b5; is the permittivity of the tunnel insulating film of the memory cell, Cr indicates a coupling ratio of the memory cell, Tox indicates the thickness of the tunnel insulating film, k indicates an attenuation rate of the existence probability when the charges are detrapped and is represented as k=(2mE/(h/2&#x3c0;)), m indicates the mass of the electron, E indicates an energy level of the trap of the tunnel insulating film, h indicates a Planck's constant, and &#x3c0; indicates a circumference ratio).

Method of evaluating a semiconductor storage device

A cell characteristic measuring circuit for a nonvolatile memory is provided which, with the use of one circuit can satisfy both the requirements necessary to a characteristic evaluation using a cell array TEG and reliability evaluation using a memory circuit. The measuring circuit comprises a cell array having a matrix array of NAND strings each having a plurality of series-connected cell transistors, a first select gate and a second select gate connected in series. The cell array is divided into a plurality of blocks, a select gate line is connected to the gates of first select gates in each NAND string in the same block, and a word line is connected to the control gates of cell transistors in each row. A first external terminal is connected to a selected bit line, and a second external terminal is connected to each word line in the plurality of blocks.

Cell characteristic measuring circuit for a nonvolatile semiconductor

After data is written into a desired memory cell of a memory cell array, a booster circuit verifies the threshold voltage of the memory cell in which data is written. An erase timing signal generation circuit connected to a control circuit generates a timing signal for a short period of time when a memory cell having a threshold voltage higher than the power supply voltage. An erasing voltage generation circuit applies a negative erasing voltage to the memory cell in which data is written for a short period of time according to the timing signal supplied from the erase timing signal generation circuit to slightly lower the threshold voltage of the memory cell so as to prevent the excessive writing.

Non-volatile semiconductor memory device capable of preventing

An EEPROM in which a select transistor to which any memory cell not selected is turned off to inhibit electron injections into the floating gate of the memory cell not selected. The memory cells of the EEPROM are arranged in rows and columns in a substrate. The memory cells forming each column are connected in series. The two endmost memory cells are connected to two select transistors, respectively. The bit lines are connected to a data latch/sense amplifier, which is connected to a column decoder. The column decoder controls the bit lines. A row decoder controls select gates and control gates. A voltage-boosting circuit generates a high voltage, which is applied to the substrate and the select gates to erase data in the EEPROM, and to the control gates to write data into the EEPROM. A low-voltage controller generates a low voltage, which is applied to the select gates for turning off the select transistors of the column not selected, thereby to prevent data-writing.

Nonvolatile semiconductor memory device having a small number of

A memory cell transistor includes a semiconductor substrate, a N-type source region, a N-type drain region, a control gate and a P.sup.+ -type emitter region, which is formed in the surface region of the drain region. An insulating film overlies the source region, the drain region, the emitter region, and the control gate. A contact hole is formed in the insulating film so that the surface of the emitter region is exposed. An emitter electrode is formed in and around the contact hole. A PNP vertical bipolar transistor is constituted by the semiconductor substrate serving as a collector region, a P.sup.+ -type buried layer serving as a collector contact, and the drain region serving as a base region.

Nonvolatile semiconductor memory circuit with high speed read-out

A nonvolatile semiconductor memory device has n.sup.+ -type source and drain regions formed in the surface of a p-type semiconductor substrate, a floating gate formed above and insulated from a channel region provided between the source and drain regions, and a control gate formed above and insulated from the floating gate. The memory device further has a capacitor provided between the control gate and drain region.

Nonvolatile semiconductor memory device

In a reduced projection type step- and repeat-exposure apparatus of the present invention, the angle of inclination of an exposure area on the wafer is first detected, and then corrected on the basis of the detected value. This measurement corrects the inclination of the exposure area. Hence, high precision patterning can be realized, even if an optical system having a small focus margin is used.

Reduced projection type step- and repeat-exposure apparatus

A method of manufacturing a nonvolatile semiconductor memory device having a gate oxide layer including a relatively thin silicon dioxide layer. This gate oxide layer including the thin silicon dioxide layer is formed by the steps of forming the gate oxide film on a semiconductor element region in a silicon substrate; removing a portion of the gate oxide film to expose a portion of the silicon substrate; implanting impurity ions in the exposed portion of the substrate to an extent that a peak concentration of the impurity ions exceeds a solid solution limit at a temperature of the following thermal annealing step; activating the implanted impurity by thermal annealing so as to form a high impurity concentration layer and thermally oxidizing a surface of the high impurity concentration layer to form the thin silicon dioxide layer.

Method of manufacturing nonvolatile semiconductor memory device by

A method for producing a semiconductor device comprises a step of forming a first gate insulation layer on a portion of a single crystal silicon substrate and forming a floating gate of polycrystalline silicon on the first gate insulation layer, a step of forming an oxide layer on the exposed portion of the substrate and on the floating gate, and a step of forming a control gate on the floating gate through the oxide layer. In the formation of the oxide layer, a nitride pattern layer is formed on the floating gate, the entire structure is oxidized by using the nitride pattern layer as a mask, thus forming a protective layer on the exposed portion of the substrate, the nitride pattern layer is removed, and the entire structure is again oxidized, thus forming a second gate insulation layer on the floating gate.

Method for producing a semiconductor device with a floating gate

There is disclosed a method of manufacturing a semiconductor device comprising a step of forming an isolation film having a patterned hole on a major surface of a semiconductor substrate of a P conductivity type, the wall of the isolation film defining the patterned hole having a large step, a step of forming a polysilicon layer on the major surface of the structure, a step of forming a first interlaid SiO.sub.2 layer on the polysilicon layer, a step of patterning the SiO.sub.2 layer and polysilicon layer using reactive ion etching process, thereby forming on the region of the substrate a gate electrode and a first SiO.sub.2 film superposed thereon, the continuous side wall of the gate electrode and first SiO.sub.2 film having a large step, a step of implanting an impurity ion into the substrate using the first SiO.sub.2 film as a mask, thereby forming an impurity diffused region of an N conductivity type in the substrate, a step of forming a second interlaid SiO.sub.2 layer on the major surface of the structure, and a step of applying reactive ion etching to the second SiO.sub.2 layer, thereby forming a contact hole in the second SiO.sub.2 layer leading to the impurity diffused region, while leaving part of the second SiO.sub.2 layer on the side walls of said isolation film, gate electrode and first SiO.sub.2 film.

Method of making high density dielectric isolated gate MOS transistor

In a memory device, a plurality of memory cells are connected to bit line pairs. A precharge circuit is controlled by a chip enable signal during a stand-by state and by an address transition detector signal during an active state, to charge the bit line pairs up to a given power source voltage.

Memory device resistant to soft errors

A semiconductor memory device has at least one memory cell which includes first and second tunnel diodes connected in series in a forward-bias direction between first and second power source terminals. The first and second power source terminals are held at constant potentials. A switching MOS transistor is connected at one end to a connection point between the first and second tunnel diodes. The potential at the connection point between the first and second tunnel diodes is determined by the potential at the other end of the switching MOS transistor.

Semiconductor memory device having tunnel diodes

A method for element isolation utilizing insulating materials in a semiconductor substrate is proposed. In this method an oxidizable material layer of polycrystalline silicon or the like is formed and then the oxidizable material layer is selectively oxidized, using an oxidation-proof mask thereby forming a thick oxide layer. Thereafter, the oxidation-proof mask is removed and unoxidized oxidizable material below the mask is perpendicularly etched off, leaving part of the oxidizable material which is then oxidized to form together with the thick oxide layer an element isolation. This invention further proposes a semi-conductor device having element isolation layer whose bird's beak is very small in length.

Semiconductor device and method for manufacturing the same

A method of manufacturing a semiconductor device which comprises the steps of: forming on a semiconductor substrate a layer of a material more quickly oxidizable than the semiconductor substrate; selectively oxidizing only that portion of the layer which is mounted on the element region of the semiconductor substrate; removing at least part of said oxidized layer; and wet oxidizing the retained portion of said more oxidizable material layer to provide an element-isolating oxide layer.

Growing community of inventors

Kamakura, Japan

Naohiro Matsukawa