Renesas Electronics Corporation

Nec Electronics Corporation

Nec Corporation

Naohiro Matsui

Hiroyuki Okada

Kichung Kim

Tomoaki Hirota

Takahiro Sato

Osamu Inagawa

Tatsuhiko Maruyama

A rate determination apparatusincludes a reception unitconfigured to receive a transmission frame modulated by an FSK modulation scheme, a symbol rate detection unitconfigured to detect a symbol rate based on a period of a preamble portion in the received transmission frame, a multilevel symbol detection unitconfigured to detect a multilevel-modulated multilevel symbol based on a frequency deviation in the received transmission frame, and a bit rate determination unitconfigured to determine a bit rate based on the detected symbol rate and the detected multilevel symbol. Then, the bit rate can be determined during communication.

Rate determination apparatus, rate determination method, and reception apparatus

A radio frequency signal can be received in an intermediate frequency mode suitable for radio wave reception conditions. An oscillator has a variable oscillation frequency. A quadrature demodulator includes a frequency mixer and generates an intermediate frequency signal having an intermediate frequency lower than the frequency of the radio frequency signal. An ADC receives the intermediate frequency signal passed through an analog filter and converts the received intermediate frequency signal to a digital signal. A channel selection signal processing section generates a demodulated signal from the intermediate frequency signal converted to the digital signal. A mode control section switches the operating mode of the quadrature demodulator between a zero intermediate frequency mode and a low intermediate frequency mode in accordance with the radio wave reception conditions.

Radio receiver and intermediate frequency selection method

An RFVGA variably controls a gain according to an RFVGA gain control signal and amplifies and outputs a reception signal. A low-pass filter filters a signal output from a frequency converter. An OFDM demodulator generates a digital signal based on an output signal from the low-pass filter. A power detection evaluation circuit controls the RFVGA gain control signal based on a voltage value (DET) of the RFVGA gain control signal or a voltage value (DET) of the output signal from the RFVGA, and a voltage value (DET) of an output signal from the low-pass filter and a voltage value (DET) of an intermediate node of the low-pass filter.

Receiver and method for gain control

A harmonic rejection mixer converts a frequency of a radio frequency signal by using a first to a third local signals (LOs) whose phases are different from each other, and the harmonic rejection mixer includes a phase difference detection circuit for detecting a phase difference between the first LO and the second LO, a phase difference detection circuit for detecting a phase difference between the first LO and the third LO, a phase adjustment circuit for adjusting the phase of the second LO so that the phase difference detected by the phase difference detection circuit becomes a first phase difference, and a phase adjustment circuit for adjusting the phase of the third LO so that the phase difference detected by the phase difference detection circuit becomes a second phase difference. It is thereby possible to achieve high precision harmonic rejection characteristics.

Harmonic rejection mixer and phase adjustment method thereof

In a wireless communications system, it is important to realize a limiter operation by which a differential amplifier for amplifying a local signal may stably supply an output signal having a constant amplitude. However, when a signal handled by the system has a high frequency, a gain of the differential amplifier is reduced and the limiter operation may not be performed appropriately. The differential amplifier is configured employing a double cascode connection to enhance an output impedance, an upper transistor of the double cascode connection realizes enhancement in gain and frequency characteristics based on a positive feedback signal, and a lower transistor of the double cascode connection controls an operating point and suppresses an allowable output voltage range by operating in a linear region and based on a negative feedback signal to facilitate the limiter operation.

Differential amplifier

Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal. The circuit further includes a binarization circuit for receiving the output signal of the differential-input/single-ended output amplifier and comparing the output signal with a threshold voltage to thereby binarize and output the signal. The threshold voltage is adjustably set.

High-frequency signal detector

There is provided a variable-gain amplifier, including two cascode amplifiers and an attenuator. The cascode amplifiers are mutually connected in parallel via the attenuator.

Variable-gain amplifier

A gain variable amplifier according to an embodiment of the present invention includes: an amplifier circuit amplifying an input signal with a variable gain; and a gain control circuit controlling the gain of the amplifier circuit based on a gain control signal, in which the amplifier circuit includes: an amplifying element amplifying the input signal; an output element series-connected with the amplifying element and outputting a signal amplified with the amplifying element; and a bias circuit changing a potential at a node between the output element and the amplifying element based on the gain control of the gain control circuit.

Gain variable amplifier

BPF having a band width of &verbar;reference signal f -mixer output signal f &verbar; is connected to a phase comparator. When an output signal corresponding to the passage of this band width has been obtained, a changeover switch is turned OFF. Upon detection such that the PLL circuit is unlockable, an output signal is obtained from an offset differential pair circuit, the changeover switch is turned ON, and the time constant of LPF is reduced to shorten the lock-up time, and the voltage applied to VCO is made larger than the usual voltage. By virtue of this construction, a PLL circuit of an analog system can be realized which can shorten the lock-up time and, in addition, can reduce noise and spurious harmonics.

PLL circuit with shortened lock-up time

A phase-comparison circuit includes (a) a first PNP transistor, (b) a second PNP transistor, (c) a third NPN transistor electrically connected to both a collector of the first PNP transistor and a base of the second PNP transistor, and (d) a constant current source electrically connected to an emitter of the third NPN transistor. The phase comparison circuit compensates for an offset current between a reference current and an output current, and as a result, can properly operate at a low voltage.

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Kanagawa, Japan

Naohiro Matsui