Nec Corporation

Nec Electronics Corporation

Sony Semiconductor Solutions Corporation

Sony Corporation

Tetsuya Muraoka

Naohiko Kimizuka

Kiyotaka Imai

Yuri Masuoka

Toshiyuki Iwamoto

Takuji Matsumoto

Ichiro Yamamoto

Hirohito Watanabe

Kan Shimizu

Jun Ogi

Motofumi Saitoh

Yoshiro Goto

Yuri Kato

Yoshihisa Matoba

Hiroshi Ito

Nobutoshi Fujii

Shinya Ito

Koichiro Zaitsu

Shuji Manda

Tadahiko Horiuchi

Shinichi Miyake

Ayuka Tada

Tomohiko Kudo

Masayuki Terai

Keiji Ohshima

Keiichi Nakazawa

Hirofumi Yamashita

Junpei Yamamoto

Shigetaka Mori

Shinji Nakagawa

Shintaro Okamoto

Yohei Hiura

Yasushi Hamamoto

Tomoki Kambe

Ryo Ogata

Tatsuki Miyaji

Yui Yuga

Yuri Yasuda

A semiconductor device, a semiconductor device manufacturing method, and an image capturing device capable of suppressing variations in transistor characteristics. The semiconductor device includes a semiconductor substrate, and a field effect transistor. The field effect transistor includes a semiconductor region having a channel, a gate electrode covering the semiconductor region, and a gate insulating film. The semiconductor region has a top face, and a first side face at one side of the top face in a gate width direction of the gate electrode. The gate electrode has a first part facing the top face over the gate insulating film, and a second part facing the first side face over the gate insulating film. A first end face of the first part and a second end face of the second part are flush at at least one end of the gate electrode in a gate length direction.

Semiconductor device and semiconductor device manufacturing method, and image capturing device

To achieve decreased noise and improved sensitivity by reducing parasitic capacitance in a charge detection sensor. The charge detection sensor includes a detection element, a detection electrode, and a contact. The detection element is provided on one surface of a semiconductor substrate and detects a charge. The detection electrode is provided on another surface different from the one surface of the semiconductor substrate. The contact penetrates the semiconductor substrate and electrically connects the detection electrode and the detection element. Since no wiring layer is formed between the detection element and the detection electrode, the parasitic capacitance is reduced.

Charge detection sensor and potential measurement system

An imaging element and device configured for reduced image quality deterioration are disclosed. In one example, a pixel unit of the imaging element includes a selection transistor and an amplification transistor each constituted by a multigate transistor. The selection transistor and amplification transistor may be a FinFET that includes a silicon channel having a fin shape. Moreover, gates of the selection transistor and the amplification transistor may be formed on an identical silicon channel having a fin shape. Furthermore, for example, an ion having a smaller thermal diffusivity than a thermal diffusivity of boron or phosphorous is injected into the silicon channel of the selection transistor. In addition, for example, a work function of a material of a gate electrode of the selection transistor is different from a work function of a material of a gate electrode of the amplification transistor.

Imaging element and imaging device with selection and amplication transistor gates formed on same silicon channel

There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.

Solid-state imaging device

Imaging element and imaging device

To provide an electric potential measuring device that can further improve evaluation quality. Provided is an electric potential measuring device including a plurality of readout electrodes arranged in an array form and each configured to detect an electric potential of an action potential generation point generated by an action of a cell, an insulating member, a reference electrode configured to detect a reference potential, and an amplification section configured to obtain a potential difference between a detected electric potential based on the readout electrode and a detected electric potential based on the reference electrode, in which the readout electrode has a covered region where the insulating member is stacked on the readout electrode and an opened region where the insulating member is not stacked on the readout electrode, and the readout electrode has, in the opened region, at least one high portion with high height and/or at least one low portion with low height, with a stacking surface of the readout electrode with the insulating member as a standard.

Electric potential measuring device and method for manufacturing electric potential measuring device

In a solid-state imaging element provided with a differential pair of transistors, noise of a signal from the differential pair is reduced. The semiconductor integrated circuit includes a pixel circuit and a pair of TFETs (Tunnel Field Effect Transistors). In the semiconductor integrated circuit, the pixel circuit photoelectrically converts incident light to generate a pixel signal. Further, in the semiconductor integrated circuit, the pair of TFETs amplifies the difference between the pixel signal generated by the pixel circuit and a predetermined reference signal that changes with time, and outputs the amplified difference as a differential amplification signal.

Semiconductor integrated circuit and imaging device

A solid-state imaging device comprising a semiconductor substrate; a logic circuit region having a first gate electrode; a pixel region having a plurality of pixel units, each which includes at least one second gate electrode; a first gate insulating film forming between the first gate electrode in the logic circuit region and the semiconductor substrate; a second gate insulating film forming between the second gate electrode in the pixel region and the semiconductor substrate; a first insulating layer covering the first gate electrode and the second gate electrode; and an offset spacer on a sidewall of the first gate electrode being formed by etch back of the first insulating layer on the first gate electrode.

Method for manufacturing solid-state imaging device

A method is provided for manufacturing a solid-state imaging device including a semiconductor substrate having a photoelectric conversion portion, a pixel transistor region and a logic circuit region. The method includes the steps of forming a first gate electrode on the semiconductor substrate with a first gate insulating film therebetween, a second gate electrode in the pixel transistor region on the semiconductor substrate with a second gate insulating film therebetween; forming a first insulating layer to cover the first gate electrode, the second gate electrode, a floating diffusion region where a floating diffusion portion is to be formed, and the photoelectric conversion portion; and forming an offset spacer on a sidewall of the first gate electrode by etch back of the first insulating layer in a state where the photoelectric conversion portion, the pixel transistor region and the floating diffusion region are masked.

A semiconductor deviceincludes a silicon substrate, an N-type MOSFETincluding a first high dielectric constant filmand a polycrystalline silicon filmon the silicon substrateand a P-type MOSFETincluding a second high dielectric constant filmand a polycrystalline silicon filmjuxtaposed to N-type MOSFETon the silicon substrateThe second high dielectric constant filmis formed to have the film thickness thinner than the film thickness of the first high dielectric constant filmThe first high dielectric constant filmand the second high dielectric constant filmcontains one or more element(s) selected from Hf and Zr.

Semiconductor device having high dielectric constant layers of different thicknesses

Threshold voltage of a field effect transistor is successfully adjusted with a smaller dose of an impurity, as compared with a conventional adjustment of the threshold voltage only by doping an impurity into the channel region. A semiconductor devicehas a silicon substrateand a P-type MOSFETcomprising a SiON filmformed on the silicon substrate, and a polycrystalline silicon filmAny one of, or two or more of metals selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ti, Ta and W are allowed to reside at the interface 115 between the polycrystalline silicon filmand the SiON film, and concentration of the metal(s) at the interfaceis adjusted to 5&#xd7;10atoms/cmor more and less than 1.4&#xd7;10atoms/cm.

Semiconductor device

A semiconductor devicecomprises a silicon substrate, an N-type MOSFETincluding a high concentration-high dielectric constant filmformed on the silicon substrateand a polycrystalline silicon film, and a P-type MOSFETincluding a low concentration-high dielectric constant filmand a polycrystalline silicon filmformed on the semiconductor substrateto be juxtaposed to the N-type MOSFET. The low concentration-high dielectric constant filmand the high concentration-high dielectric constant filmare composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant filmis lower than that contained in the high concentration-high dielectric constant film

In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.

MOS transistor

In a semiconductor device including at least one p-channel type MOS transistor, a silicon dioxide layer is formed on a silicon substrate, and a gate electrode is formed on the silicon dioxide layer. The gate electrode silicon has a three-layered structure including a silicon-seed layer formed on the silicon dioxide layer, a silicon/germanium layer formed on the silicon-seed layer, and a polycrystalline silicon layer on the silicon/germanium layer. An average grain size of polycrystalline silicon in the polycrystalline silicon layer is at most 100 nm, and p-type impurities are substantially uniformly distributed in the gate electrode along a height thereof, and the germanium atoms are diffused from the silicon/germanium layer into the silicon-seed layer at high density.

Semiconductor device including p-channel type transistor, and production method for manufacturing such semiconductor device

Growing community of inventors

Kanagawa, Japan

Naohiko Kimizuka