Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Hewlett-packard Company

Naohiko Irie

Hiroyuki Mizuno

Naoki Hamanaka

Yusuke Kanno

Masabumi Shibata

Tony Lee Werner

Tetsuya Yamada

Takahiro Irita

Saneaki Tamaki

Motokazu Ozawa

Masayuki Kabasawa

Hisayoshi Ide

Miki Hayakawa

Takao Watanabe

Kunio Uchiyama

Takehisa Hayashi

Osamu Nishii

Tetsuya Mochida

Tetsuhiko Okada

Takanobu Tsunoda

Hiroaki Shikano

Yasuhiro Ishii

Chih-Jui Peng

Atsushi Nakajima

Youichi Tanaka

Motoyasu Terao

Koichiro Ishibashi

Atsushi Ito

Riichiro Takemura

Tsuyoshi Tanaka

Hideyuki Matsuoka

Rajiv Gupta

Yoshitaka Sasago

Norikatsu Takaura

Fumio Arakawa

Toshio Okochi

Daisuke Yokota

Yooichi Shintani

Hideya Akashi

Mitsuru Inoue

Kazunori Kuriyama

Yoshikazu Tanaka

William S Worley, Jr

Frederic C Amerson

Toru Shonai

B Ramakrishna Rau

Sivaram Krishnan

Hiroshi Kurokawa

Satoshi Misaka

Margaret Rose Gearty

Jackie Andrew Freeman

Kazutaka Sakai

Keisuke Toyama

Shisei Fujiwara

Sebastian Haviuj Ziesler

Junji Inaba

Masahiro Ohmiya

Katsuto Shimizu

In a control monitoring system in which an information system is connected with a control system, the control system includes a control device that performs at least one of control and monitoring of a control target, a computer that performs a process related to the control or the monitoring, and a gateway device that relays a communication message between the control device and the computer. The gateway device acquires a predetermined state index related to a first communication message when the first communication message is received from the computer, determines whether or not a predetermined execution condition is satisfied based on the state index, transmits a second communication message based on the received first communication message to the control device when the execution condition is satisfied, and does not transmit the second communication message to the control device when the execution condition is not satisfied.

Control system in which communication between devices is controlled based on execution condition being satisfied, gateway device used in the control system, and control method for the control system

Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.

Information processing device

An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.

A bytecode accelerator which translates stack-based intermediate language (bytecodes) into register-based CPU instructions transfers plural pieces of internal information from a register file of a CPU to the bytecode accelerator by means of an internal transfer bus between the bytecode accelerator and the CPU and an input selection logic of the bytecode accelerator when the bytecode accelerator is started and transfers plural pieces of internal information in the bytecode accelerator to the register file of the CPU by means of the internal transfer bus, an output selector and an output selector selection logic of the bytecode accelerator when the bytecode accelerator ends its operation in transition between hardware processing and software processing by software virtual machine.

Handover between software and hardware accelerator

A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.

Semiconductor device with ion movement control

A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

Semiconductor integrated circuit for reducing power consumption and enhancing processing speed

A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.

Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle

In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefore for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Semiconductor integrated circuit device

A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.

Method and apparatus for event detection for multiple instruction-set processor

To enable an appropriate change of a path according to a situation of a user and a situation of a target store and the path without having a special terminal when the user of a facility utilizes the target store and an appropriate guidance, spatial recognition nodes respectively provided with a sensor and information processing equipment are installed in each location in the facility and connected via a network. The nodes recognize the position, the action and the behavior of a user of the facility. A server controlling a system manages the recognition result and constantly grasps the situation of the user. The situation of the user is recognized by the node installed at a destination and on a path, and notified to the server. The server displays appropriate path information based on the recognition result on any of plural information displays installed in the facility when the user approaches.

in-facility information provision system and in-facility information provision method

In a processor system comprising of a processor having an instruction decoder, a general registercomposed of a plurality of register areas and at least one ALU, and a Java acceleratorfor converting a Java bytecode sequence to a native instruction sequence for the processor and supplying the native instruction sequence to the instruction decoder. The Java acceleratoris composed of a bytecode translatorfor converting the Java bytecode sequence to the native instruction sequence for the processor and a register status control unitfor mapping a Java operand stack to any of the register areas of the general register and detecting a bytecode redundant for the processor. When a redundant bytecode is detected by the register status control unit, the supply of the native instruction from the bytecode translatorto the instruction decoderis inhibited.

Processor system having accelerator of Java-type of programming language

In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Standard cell for a CAD system

A mechanism of making a low standby current caused by power off compatible with a fast return operation from a standby caused by an interrupt is realized. An information processing device has a first area that includes a central processing unit and peripheral circuit modules, a second area having information holding circuits for holding values of registers contained in the peripheral circuit modules, and a first power switch for controlling supply of a current to the first area. When the information processing device operates in a first mode, an operating current is supplied to the first area and the second area. When the information processing device operates in a second mode, the first power switch is controlled so that the supply of the current to the first area can be shut off, and the supply of the current to the second area is continued.

Disclosed here is an information processing system capable of recognizing actions and circumstances of a user with respect to both space and time as a 'situation' to recognize the user's request using a plurality of sensing nodes that work cooperatively with each another, thereby responding autonomously to the user's request according to the recognition results. The plurality of sensing nodes and a responding device are disposed in a target space to build up a network for recognizing the situation in the target space. And, a plurality of recognition means are used to recognize the situation with respect to both space and time related to the existence of the user. And, an integral processing portion (master) is selected from among the plurality of sensing nodes, thereby dispersing the system load. If there are a plurality of users, the system can make recognition in accordance with the request of each of those users.

Multi-sensing devices cooperative recognition system

When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

Semiconductor device

Growing community of inventors

Kokubunji, Japan

Naohiko Irie