Kabushiki Kaisha Toshiba

Naohiko Hirano

Kazuhide Doi

Yoichi Hiruta

Takashi Okada

Yasuhiro Yamaji

Chiaki Takubo

Masayuki Miura

Eiichi Hosomi

Hiroshi Tazawa

Koji Shibasaki

Tsutomu Nakazawa

Katsuto Katoh

Akihiro Mase

Yoshihiro Atsumi

A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first insulating film. The conductive layer and the barrier metal layer are patterned by a single mask. A second insulating film is formed on the resultant structure. A second opening portion is formed in the second insulating film at a position different from that of the first opening portion. A solder bump or metal pad is formed on the barrier metal layer in the second opening portion. The position of the solder bump or metal pad is defined by the second opening portion.

Flip-chip connection type semiconductor integrated circuit device

A plurality of bumps formed of low melting metal are disposed on the surface of the peripheral portion of a semiconductor substrate. Those bumps which are included in the above bumps and formed on each corner portion of the semiconductor chip are connected to a power supply wiring and a ground wiring used as a power supply wiring. The other bumps disposed in position other than the corner portions are connected to a signal wiring.

Flip-chip connecting type semiconductor device

In a flip chip mounting type semiconductor device, on a corner portion of a chip subjected to flip chip mounting, a gate region for injecting a sealing member filled between a mounted board and the chip is arranged. In this semiconductor device, a semiconductor element has a plurality of bumps formed on the peripheral portion on a major surface along each side, a plurality of pad electrodes are formed on the major surface of the circuit board, and the pad electrodes join the bumps. A resin sealing member is filled between the semiconductor element and the circuit board. A gate region through which the resin sealing member is injected is formed on a corner portion of the semiconductor element. In the gate region, no bump is formed, or bumps are arranged at intervals smaller than that in another region. For this reason, the resin uniformly enters the space between the semiconductor element and the circuit board through the gate region.

Flip chip mounting type semiconductor device

An Al layer which serves as a lead-out electrode is formed on a semiconductor chip. An insulating layer is formed on the semiconductor chip and the Al layer. The insulating layer has an opening formed in that portion thereof which is located on the Al layer, thereby exposing a portion of the Al layer. A multi-level metal layer (barrier metal layer) is formed on the exposed portion of the Al layer and on that portion of the insulating layer which is located along the edge of the opening. A metallic nitride region is provided between a first-level metal layer in the multi-level metal layer and the insulating layer so as to be selectively formed at or under a peripheral portion of the first-level metal layer. A bump electrode is provided on the multi-level metal layer. The resultant semiconductor device is mounted on a circuit board by flip chip bonding, with the bump electrode interposed therebetween.

Connecting electrode portion in semiconductor device

A semiconductor device according to the present invention includes a resistant heating element as a temperature regulation means on a circuit board. A semiconductor chip of the device is connected to the circuit board through connecting electrodes. A difference in temperature between the semiconductor chip and circuit board is kept at a fixed value by controlling the resistant heating element.

Semiconductor device having temperature regulation means formed in

Signal wiring layers are formed between a power supply layer and a ground layer, which have conductor patterns each constituted by a plurality of parallel strip-shaped conductors. The above layers are isolated from each other by insulating layers. The signal wiring layer has wires which are arranged in parallel with the parallel strip-shaped conductors of the conductor pattern of the power supply layer, and the signal wiring layer has wires which are arranged in parallel with the parallel strip-shaped conductors of the conductor pattern of the ground layer.

Multilayer wiring structure for attaining high-speed signal propagation

A semiconductor device includes a semiconductor chip which is connected to a circuit substrate via solder bumps by flip-chip connection, a first encapsulant having a large Young's modulus and filling a space between the semiconductor chip and the circuit substrate in the central portion of the semiconductor chip, and a second encapsulant having a small Young's modulus and filling a space between the semiconductor chip and the circuit substrate in the peripheral portion of the semiconductor chip. A method for manufacturing the semiconductor device includes flowing the second encapsulant into position, but not the first encapsulant.

Flip-chip semiconductor devices having two encapsulants

A heat sink is attached to a semiconductor element functioning as an exothermic element, which is mounted on a circuit board and has a predetermined allowable power consumption, thereby cooling the semiconductor element. A semiconductor element having a lower allowable power consumption than the semiconductor element having the predetermined power consumption, which is hardly exposed to a cooling air flow cooled via the heat sink, is connected to a heat conductive auxiliary member connected at one end to the heat sink. Thus, the heat radiation efficiency of the semiconductor element having the lower allowable power consumption is enhanced.

Semiconductor apparatus capable of cooling a semiconductor element with

A semiconductor device includes a rectangular wiring substrate and a plurality of semiconductor elements having connecting electrodes such as projecting electrodes connected to the wiring substrate. Even though the wiring substrate is deformed, the semiconductor elements and connecting electrodes are prevented from being broken, thereby maintaining the reliability of the semiconductor device for a long period of time. A buffer region constituted by grooves is formed in that middle part of the undersurface of the rectangular wiring substrate which is located between both the long sides of the wiring substrate and between both the short sides thereof. The semiconductor elements are formed outside the buffer region. The connecting electrodes of the semiconductor elements are connected to a wiring pattern on the surface of the wiring substrate, with the result that the semiconductor elements are mounted on the wiring substrate. The deformation of the buffer region absorbs a deformation of that part of the wiring substrate which is located near the semiconductor elements mounted on the wiring substrate thereby to protect the semiconductor elements.

Semiconductor device and method of manufacturing the same

A semiconductor chip is packaged within film carriers which serve as the enclosure of the semiconductor chip. The finished semiconductor device is flexible, bendable, and very thin. In manufacturing this semiconductor device, the process of laminating film carriers, the process of electrically connecting the semiconductor chip and film carriers, and the process of sealing the semiconductor chip, can be performed at the same time, shortening the manufacturing time and reducing manufacturing cost.

Semiconductor device of multichip module-type

The present invention provides a multilayer ceramic package, which comprises a conductive layer, formed like a square layer, applying a power voltage V.sub.DD or a ground voltage V.sub.SS to a semiconductor device, and having a square hole in its central portion, a plurality of inner leads connected to the conductive layer at the inner portion of the conductive layer, and a plurality of outer leads connected to the conductive layer at the outer portion of the conductive layer, wherein if a first contact point between the inner lead and the conductive layer, a second contact point between the outer lead and conductive layer, a distance between adjacent two first contact points is C.sub.1, a distance between adjacent two second contact points is C.sub.2, a shortest distance from the first contact point to the second contact point is h, both C.sub.1 /h and C.sub.2 /h are 3/8 or less.

Growing community of inventors

Kawasaki, Japan

Naohiko Hirano